Arnulf Leuther

This letter presents a receiver (Rx) monolithic microwave-integrated circuit (MMIC) that covers a minimum frequency range from 140 to 333 GHz. The MMIC is fabricated in a 35-nm gate-length InGaAs metamorphic high-electron-mobility transistor (mHEMT) technology. The Rx MMIC comprises a low-noise amplifier, an local oscillator (LO) buffer driver, and a fundamental mixer. The amplifiers share the same distributed-amplifier core. The fundamental mixer is based on a balanced resistive high-electron-mobility transistor topology and achieves a conversion gain (CG) as high as −8.2dB. The Rx MMIC is designed to achieve an upper band edge of more than 400 GHz. Across the measured frequency range from 140 to 333 GHz, the Rx exhibits an average CG of 16.1dB and an average noise figure (NF) of 6.8 dB, ranging from 4.5 to 8.7 dB. To the best of the authors’ knowledge, this is the first Rx MMIC covering a bandwidth of more than 190GHz, while achieving an average NF of 6.8 dB.

In this article, the monolithic integration of an adaptive local oscillator (LO) leakage cancellation circuit together with an unbalanced resistive in-phase and quadrature (IQ) high-electron-mobility transistor (HEMT) mixer is presented. The proposed calibration algorithm for the cancellation signal is tolerant against any nonideal component responses. A typical LO-to-radio frequency (RF) isolation of 60 dB is achieved, which corresponds to a LO leakage of −55 dBm at saturated mixer operation. To the best of the authors’ knowledge, this is the highest reported performance of a monolithic approach beyond 100 GHz. As part of this work, the leakage cancellation’s sensitivity with regard to environmental changes is investigated. Furthermore, a semi-balanced IQ mixer is implemented in the same technology. An analytic equation for its LO suppression as a function of amplitude and phase imbalance is derived. Detailed comparisons of the output spectra of both mixers, their two-tone intermodulation distortion characteristics, and noise figures (NFs) complement this study.

We present enhancement- and depletion-mode digital logic gates and circuits with back-gate biasing in a Four-pole high-electron-mobility transistor on Silicon technology. This work uses a 20-nm gate-length InGaAs HEMT-on-Si with the option to place an electron-beam-lithography defined back-gate below the InGaAs channel by wafer bonding. By applying back-gate bias, the threshold voltage is modulated to convert normally depletion-mode devices into enhancement-mode devices, without altering the physical structure or processing steps. The back-gated RF transistors are used directly to implement digital logic gates such as NOT, NAND, and NOR, as well as a D-LATCH circuit, and are demonstrated using the E/D logic approach. Additionally, the effect of back-gate biasing on the power consumption of logic gates is analyzed. The proposed circuits provide the opportunity to integrate logic components with state-of-the-art RF circuits monolithically.

This letter presents a distributed amplifier (DA) monolithic microwave integrated circuit (MMIC) achieving a bandwidth (BW) of range-phrase = –4420with a small-signal gain of 11 ± 2. This sets a new BW record for ultrawideband amplifier MMICs. DA MMIC utilizes the Fraunhofer IAF 20gate-length InGaAs-on-Si high-electron-mobility transistor (HEMT) technology and features ten gain cells. Each cell contains an RF cascode using two-finger transistors with a total gate width (TGW) of 16. The measured noise figure (NF) is in the range of range-phrase = –3.27.7(<202) and range-phrase = –2.86.7when biased for low-noise (LN) conditions. Especially, the high-frequency NF shows a remarkable performance, e.g., achieving an average NF of 4.7;5(range-phrase = –163202) for LN and standard bias, respectively.

This paper highlights two 8×1 transmitter and receiver front-ends which are individually composed of two in-parallel assembled four-channel submillimeter-wave monolithic integrated circuits (S-MMICs) operating at 400 GHz. These S-MMICs integrate frequency multipliers, mixers, and amplifiers as well as on-chip antennas. They are manufactured on a 35 nm metamorphic high-electron-mobility transistor technology. The included to-the-broadside radiating on-chip antennas allow for simplified assembly on a printed circuit board upon which two 4×1 transmitter or receiver S-MMICs are placed in parallel. Furthermore, a separate multiplier-by-four is integrated allowing for a low-frequency input drive in the range from 22.50 to 26.25 GHz. The operational frequency range of the front-ends is from 360 to 420 GHz. Both on-wafer and front-end level measurements are shown, including the farfield pattern characterization of the respective metastructure-based on-chip antennas. With all eight channels of the transmitter front-end active, a radiated output power of at least 10 mW is achieved for the frequency range from 390 to 420 GHz setting the state-of-the-art.

A unified, scalable Schottky diode model has been developed. Based on two different high-electron-mobility transistor (HEMT)-technologies from Fraunhofer IAF, test structures with diodes in series configuration were designed and manufactured. The geometrical dimensions of the Schottky contact are varied among the test structures to extract geometrical dependencies of the device parameters. All test structures were characterized by means of dc $I$ – $V$ curves and scattering parameters. From the obtained data, an equivalent circuit representation was derived. A new method to determine the junction capacitance is presented which is independent of the series resistance. If the latter is not negligible compared with the junction resistance at forward bias, this method proves to be more precise than a calculation from admittance parameters. In addition, this method allows to extract the frequency-and bias-dependent series resistance what has been subjected to significant simplifications in the past. For means of verification, the model was checked against the measured scattering parameters. Furthermore, a diode ring mixer was designed, manufactured, and characterized which uses four HEMT-based Schottky diodes with geometrical dimensions that differ from the evaluated test structures. A comparison of the measurement and a simulation based on the proposed model demonstrates excellent agreement at D -band frequencies.

This letter presents two distributed low-noise power-amplifier (LNPA) monolithic microwave integrated circuits (MMICs). The two amplifiers (DA1 and DA2) target the WR4.3 (170–260 GHz) and WR3.4 bands (220–330 GHz) as a minimum operating bandwidth (BW). The MMICs are realized in the Fraunhofer IAF 35-nm InGaAs mHEMT technology. Both amplifiers yield a small-signal gain of more than 20 dB from 110 GHz up to the corresponding upper band edges (265 and 335 GHz) and an average noise figure (NF) of 4.5 dB (110–216 GHz). Furthermore, DA1 delivers a saturated output power ( P sat) of 12.4–15.2 dBm with a power-added efficiency (PAE) of 3.4%–6.2% (160–255 GHz). DA2 exhibits a P sat of 10–14.5 dBm (210–335 GHz). To the best of the authors’ knowledge, DA1 and DA2 present the best NF and P sat over the full WR4.3 and WR3.4 bands, respectively.

This paper presents an ultra-wideband vector modulator using an attenuator-based amplitude modulation covering the frequency range from 100 to 300 GHz. The proposed MMIC achieves up to a 6-bit phase resolution. This work depicts the individual components design, the entire MMIC, architecture as well as calibration used that enhance the chip performance. The design is implemented using a 35 nm InGaAs metamorphic HEMT process and achieves an RMS phase error down to 1 $^\circ$ , and an RMS amplitude error of 0.5 dB after calibration. The chips, including RF and control pads, consume 1 × 1.25 mm $^{2}$ .

This article reports on the design of $C$ -band (4–8 GHz) monolithically integrated low-noise amplifiers (LNAs) in a 50-nm metamorphic high-electron-mobility transistor (mHEMT) technology with low-dc-power consumption dedicated to cryogenic operation in large receiver arrays. Two LNA monolithic microwave-integrated circuits (MMICs) are investigated: one two-stage design (LNA 1) targeting the $C$ -band, which has been designed as a stand-alone and as a four-channel MMIC to demonstrate the ability to achieve higher integration levels. The second amplifier (LNA 2) is a three-stage design focusing on 6–9 GHz, but it can also be used from 4–9 GHz with only minor performance degradation. LNA 1 achieves an average in-band noise temperature of 2.7 K with 31 dB of gain when operated at 10 K with optimal noise bias (7.78-mW dc-power consumption). The power consumption of LNA 1 can be reduced to 0.77 mW with an average noise of 3.8 K and 23.7 dB of gain. LNA 2 provides 44.5 dB of small-signal gain and 3.3-K average noise temperature between 4 and 9 GHz (2.9 K between 6 and 9 GHz) at 10 K and optimal noise bias (5.57 mW). When the dc-power consumption of LNA 2 is reduced to 1.34 mW, 35.4 dB of small-signal gain and 4.4 K of average noise temperature are preserved. To the best of the authors’ knowledge, LNA 1 demonstrates both the lowest noise temperature and dc-power consumption among monolithically integrated $C$ -band LNAs at cryogenic temperatures.