Nagendra Krishnapura

This article presents a 1.75-GS/s single-channel 7-bit successive approximation register (SAR) analog-to-digital converter (ADC) that is based on loop-unrolled architecture with N-comparators for N-bits. A memory-less fully asynchronous SAR is proposed to lower power consumption and reduce design complexity. A double-tail feed-backward (DTFB) dynamic comparator is proposed to meet the required speed and minimize thermal noise, which is a critical parameter for a 7-bit SAR ADC. The prototype ADC is implemented in a 3-nm CMOS process. The ADC achieves an SNDR/SFDR of 37/49 dB at Nyquist, 0.00055-mm $^{\text{2}}$ area, and consumes 0.69-mW power. This leads to a best-in-class Walden figure of merit (FoM $_{\mathbf{w}}$ ) of 6.9 fJ/conv.-step and a Schreier FoM of 158 dB at Nyquist. This SAR ADC is used in a 64-way time-interleaved (TI) ADC to achieve 112-GS/s operation for use in an ADC-based 224-Gb/s PAM4 SerDes receiver.

Adapting a continuous-time delta-sigma analog-to-digital converter (ADC) for incremental operation at high sampling rates degrades the noise and distortion due to potential overload of the modulator as it comes out of reset and nonlinear residue on the reset switch due to input current flowing through it in the reset phase. It is shown that the input and DAC currents must simultaneously begin to flow through the first integrating capacitor to minimize the possibility of overload. The first integrator reset has to be released just before the start of the DAC pulse. A feedforward path must be used to ensure that the DAC output is close to the input signal from the beginning. Blocking the input current from flowing through the reset switch in the reset phase eliminates the effect of the nonlinear residue. A 320 MS/s fourth-order incremental delta-sigma ADC prototype in a 180 nm process using the above techniques has 90 dB dynamic range, 82 dB SNDR, and 84.5 dB SNR in a 2.5 MHz bandwidth. It consumes 46.3 mW from a 1.8 V supply and occupies 0.7 mm2.

This article presents a frequency synthesizer for generating quadrature local-oscillator (LO) waveforms covering an octave range of 6 to 12-GHz. It uses two voltage-controlled oscillators (VCO) to cover an octave range from 12 to 24 GHz. The VCOs employ inductor mode switching in addition to conventional capacitor switching to obtain a wide tuning range while maintaining a good phase noise figure of merit (FoM). Modulus-dependent delay (MDD) of the feedback divider increases jitter in fractional- $N$ mode. The delay change can exceed 100 ps when the number of stages in the divider chain changes. A new digital technique, which can be realized with minor modifications to the conventional digital delta-sigma modulator (DDSM), is implemented to overcome this effect. The delay change is turned into a periodic error at half the reference frequency that is then filtered by the loop filter. The prototype synthesizer in 65-nm CMOS occupies $0.54~\text {mm}^{{2}}$ and consumes 66 mW at the highest frequency from a 1-V supply, including buffers and dividers. The nominal loop bandwidth is 280 kHz. The integrated jitter is dominated by the VCOs and is 400, 300, and 500 fs in the 6 to 8-GHz, 8 to 10-GHz, and 10 to 12-GHz ranges, respectively. The worst case reference spurs are below −60 dBc and the fractional spurs are below −31 dBc.

Pseudo-logarithmic signal-strength indicators are usually realized using a chain of amplifiers with amplitude detectors at the output of each stage and summing the output of the amplitude detectors. It is shown that the same can be achieved by measuring the total supply current of a pseudodifferential self-biased CMOS inverter chain. CMOS inverters act as amplifiers, and their supply current indicates the input amplitude. Amplification and amplitude detection are combined in the same block. The supply current is measured by mirroring the current in the pass transistor of the regulator that is used to power the inverter chain. Noise floor is set by the initial stages of the chain. A 65nm prototype has a 70 dB dynamic range with ±1 dB error. It occupies 0.08mm2 and consumes 1.2mW from 1.5V. The input referred noise floor is 0.2mV rms.

This article presents a delta–sigma modulator (DSM) using a cascoded floating-inverter-based dynamic amplifier. The proposed cascoded dynamic amplifier achieves more than 50-dB dc gain while maintaining an HD3 of better than –110 dBc for signal swings less than $300~\mathrm {mV_{ppd}}$ . Compared to the previously reported two-stage floating inverter amplifier (FIA), the cascoded FIA has a lower and a process invariant input-referred noise, making it an ideal choice for high-resolution ADCs. We also show that, when such a single-stage dynamic amplifier, which has a time-varying transconductance, is used in closed-loop switched-capacitor circuits, the settling bandwidth depends on the average transconductance $G_{m,\rm avg}$ during the settling interval. A detailed analysis reveals that, when the floating inverter structure operates in weak inversion for most of the time (which is the power-efficient way to bias the amplifier), this average transconductance depends strongly on the reservoir capacitance value and only weakly on the transistor dimensions. Besides, it is less sensitive to temperature variations, unlike the transconductance of a conventional OTA biased in weak inversion. We also quantitatively derive and show that the cascoded FIA is more power-efficient than a conventional static-current biased operational transconductance amplifier. Using the cascoded FIA, a discrete-time DSM has been designed and fabricated in a 180-nm CMOS process. The modulator runs at 3.072 MHz while consuming 189 $\mu \text{A}$ from a 1.8-V supply. In a bandwidth of 24 kHz, the measured SNR/SNDR/SFDR is 96.4/96.2/114 dB, respectively.

This Special Issue of the IEEE Journal of Solid-State Circuits is dedicated to a collection of the best papers selected from the 2021 IEEE International Solid-State Circuits Conference (ISSCC) that took place on February 13-22, 2021, virtually. This issue covers papers from the Analog, Power Management, Data Converters, RF, and Wireless committees.