Ashwin Kumar Siva Kumar

This paper analyzes the stability and noise in a cascaded floating-inverter amplifier (FIA). We show that the closed-loop stability of a switched-capacitor circuit using a cascaded FIA depends mainly on the device sizes and not on the reservoir capacitors of the FIA. The closed-loop settling is similar to that when the FIA is powered by a constant voltage source. This simplifies the problem of stabilizing a cascaded FIA to stabilizing a regular cascaded amplifier, which is well-known. We also do an accurate noise analysis using results from LPTV network theory. It is known that a cascaded FIA has an increased input-referred noise when used in a closed-loop switched-capacitor circuit. We show that, in a two-stage FIA, this noise penalty factor depends on the dc gain of the first stage, which is independent of the reservoir capacitor to a first-order, and the ratio of the reservoir capacitors in the second stage and the first stage. The settling speed, on the other hand, is shown to be mainly dependent only on the last stage reservoir capacitor. Simulation results are shown to validate all the claims. Using the above results, guidelines to design a cascaded FIA are provided.

This article presents a delta–sigma modulator (DSM) using a cascoded floating-inverter-based dynamic amplifier. The proposed cascoded dynamic amplifier achieves more than 50-dB dc gain while maintaining an HD3 of better than –110 dBc for signal swings less than $300~\mathrm {mV_{ppd}}$ . Compared to the previously reported two-stage floating inverter amplifier (FIA), the cascoded FIA has a lower and a process invariant input-referred noise, making it an ideal choice for high-resolution ADCs. We also show that, when such a single-stage dynamic amplifier, which has a time-varying transconductance, is used in closed-loop switched-capacitor circuits, the settling bandwidth depends on the average transconductance $G_{m,\rm avg}$ during the settling interval. A detailed analysis reveals that, when the floating inverter structure operates in weak inversion for most of the time (which is the power-efficient way to bias the amplifier), this average transconductance depends strongly on the reservoir capacitance value and only weakly on the transistor dimensions. Besides, it is less sensitive to temperature variations, unlike the transconductance of a conventional OTA biased in weak inversion. We also quantitatively derive and show that the cascoded FIA is more power-efficient than a conventional static-current biased operational transconductance amplifier. Using the cascoded FIA, a discrete-time DSM has been designed and fabricated in a 180-nm CMOS process. The modulator runs at 3.072 MHz while consuming 189 $\mu \text{A}$ from a 1.8-V supply. In a bandwidth of 24 kHz, the measured SNR/SNDR/SFDR is 96.4/96.2/114 dB, respectively.

This brief presents a static phase offset (SPO) reduction technique through auto-zeroing in a delay-locked loop (DLL). We propose a self-calibrated, digitally programmable, sensing circuit that can measure both the polarity and the magnitude of the SPO. The SPO is suppressed by tuning a pair of digital-to-time converters (DTCs) at the input of the phase frequency detector (PFD). The proposed technique enables run-time background calibration and can suppress the SPO caused by artifacts from the PFD, charge pump, and loop filter capacitor. Monte Carlo simulation results show that the SPO in a conventional DLL implementation improves from 12.92 ps to 0.90 ps when the proposed auto-zeroing technique is employed.

Two methods are presented for implementing a multi-channel ADC using a continuous-time delta-sigma modulator (CTDSM) without resetting its states. The first is adapted from a method used with a discrete-time delta-sigma modulator. It uses a sample-and-hold (S/H) at the Nyquist rate before the modulator and an adaptive equalizer at the Nyquist rate after the modulator for flattening the equivalent frequency response and eliminate memory. The newly proposed π-shifted filter, instead of flattening the equivalent discrete-time frequency response, merely ensures that the equivalent frequency response is symmetric about ω=π/2. In the time domain, this means that the equivalent impulse response at the Nyquist rate has zero-valued odd samples ensuring no cross-talk between two multiplexed inputs. Compared to the adaptive equalizer used for flattening the frequency response, this filter consumes three times lower power while occupying half the area. A two-channel ADC is demonstrated using both the adaptive equalizer & the π-shifted filter. The ADC uses a CTDSM running at 6.144 MHz with an oversampling ratio(OSR) of 64, yielding a per-channel bandwidth of 24kHz. The prototype in 180nm achieves a peak SNR/SNDR/DR of 91.7dB/84.9dB/98dB and consumes 1.33mW per channel with adaptive equalizer. The SNR/SNDR/DR is 90.5dB/83.7dB/97dB with a power consumption of 0.86mW per channel with the π-shifted filter.

A new method is proposed for converting any continuously running discrete-time delta-sigma modulator to a multi-channel ADC by modifying only the digital filters. The two input channels are multiplexed and fed to the modulator. The cross-talk that would exist, if the output of the decimation filter is demultiplexed directly, is canceled using a modulated-sinc-sum digital filter, operating at the downsampled rate. This technique avoids reset that is required in incremental ADCs and the input sample-and-hold that is required in previously proposed techniques for multi-channel conversion without reset. A prototype two-channel ADC clocked at 6.144 MHz with a per-channel bandwidth of 22 kHz is demonstrated in a 180 nm CMOS process. It consumes 1.53 mW/channel including the digital filters and achieves a peak SNR/DR of 94.4 dB/98.5 dB, while restricting the inter-channel cross-talk to less than −94 dBc.

This paper presents new techniques to obtain sample-by-sample analog-to-digital conversion using a delta- sigma modulator (DSM) without resetting the modulator or the decimation filter. It is shown that memoryless A/D conversion without reset can be realized using a discrete-time DSM with a signal transfer function (STF) of unity and a Nyquist M-band decimation filter running at the oversampled rate. It is also shown that a delta-sigma ADC preceded by a sample-and-hold at the Nyquist rate is a linear, time-invariant system at the Nyquist rate. This relaxes the constraint on the STF and allows using a multi-rate decimation filter and an equalizer at the Nyquist rate to significantly lower the power in the digital filters. Crosstalk suppression, which is limited by analog imperfections when a fixed-coefficient equalizer is used, is shown to be substantially improved using an adaptive equalizer at the Nyquist rate. A 180-nm prototype operating at 32 MHz and an OSR of 32 demonstrates two-channel operation with crosstalk below 89 dB. It consumes 18.2 mA from a 1.8-V supply, occupies 3.86 mm ² and has DR/SNR/SNDR of 84.2/82.5/80.1 dB.

Memoryless delta-sigma ADCs can be implemented without resetting the modulator or decimation filter states using a modulator with unity STF, a Nyquist decimation filter and a front-end sample-and-hold. A previous implementation used a separate active sample-and-hold circuit using an opamp which contributed significantly to the power consumption, noise and distortion of the ADC. A passive alternative which eliminates all these shortcomings is proposed in this work. It is based on replicating the input capacitor of the delta-sigma modulator, sampling the input on all of them, and discharging them successively into the first integrator of the modulator. This technique is demonstrated with a 2 channel prototype simulated in a 180nm CMOS process. The prototype uses a 3rd order CIFF loop filter and a 4-bit quantizer, operates at 64 MHz, and has a per-channel bandwidth of 500 kHz. It consumes 20mA from a 1.8V supply, which is only 60% of the power consumed by a comparable system with a dedicated active sample-and-hold. The maximum SNR is 85 dB and the inter-channel crosstalk, limited by capacitor mismatch is 96 dB.