Byoung-Soo Choi

This paper presents the effects of offset pixel aperture width on the performance of monochrome (MONO) CMOS image sensors (CISs) for a three-dimensional image sensor. Using a technique to integrate the offset pixel aperture (OPA) inside each pixel, the depth information can be acquired using a disparity from OPA patterns. The OPA is classified into two pattern types: Left-offset pixel aperture (LOPA) and right-offset pixel aperture (ROPA). These OPAs are divided into odd and even rows and integrated in a pixel array. To analyze the correlation between the OPA width and the sensor characteristics, experiments were conducted by configuring the test elements group (TEG) regions. The OPA width of the TEG region for the measurement varied in the range of 0.3–0.5 μm. As the aperture width decreased, the disparity of the image increased, while the sensitivity decreased. It is possible to acquire depth information by the disparity obtained from the proposed MONO CIS using the OPA technique without an external light source. Therefore, the proposed MONO CIS with OPA could easily be applied to miniaturized devices. The proposed MONO CIS was designed and manufactured using the 0.11 μm CIS process.

In this paper, we propose an averaging pixel current adjustment technique for reducing fixed pattern noise (FPN) in the bolometer-type uncooled infrared image sensor. The averaging pixel current adjustment technique is composed of active pixel, reference pixel, and calibration circuit. Polysilicon resistors were used in each active pixel and reference pixel. Resistance deviation among active pixels integrated with the same resistance value cause FPN. The principle of the averaging pixel current adjustment technique for removing FPN is based on the subtraction of dark current of the active pixel from the dark current of the reference pixel. The subtracted current is converted into the voltage, which contains pixel calibration information. The calibration circuit is used to adjust the calibration current. After calibration, the nano-ampere current is output with small deviation. The proposed averaging pixel current adjustment technique is implemented by a chip composed of a pixel array, a calibration circuit, average current generators, and readout circuits. The chip was fabricated using a standard 0.35 μm CMOS process and its performance was evaluated.

A complementary metal oxide semiconductor (CMOS) image sensor (CIS), using offset pixel aperture (OPA) technique, was designed and fabricated using the 0.11-µm CIS process. In conventional cameras, an aperture is located on the camera lens. However, in a CIS camera using OPA technique, apertures are integrated as left-offset pixel apertures (LOPAs) and right-offset pixel apertures (ROPAs). A color pattern is built, comprising LOPA, blue, red, green, and ROPA pixels. The disparity information can be acquired from the LOPA and ROPA channels. Both disparity information and two-dimensional (2D) color information can be simultaneously acquired from the LOPA, blue, red, green, and ROPA channels. A geometric model of the OPA technique is constructed to estimate the disparity of the image, and the measurement results are compared with the estimated results. Depth extraction is thus achieved by a single CIS using the OPA technique, which can be easily adapted to commercial CIS cameras.

Effects of aperture size on the performance of CMOS image sensor with pixel aperture for depth extraction are investigated. In general, the aperture size is related to the depth resolution and the sensitivity of the CMOS image sensor. As the aperture size decreases, the depth resolution is improved and the sensitivity decreases. To optimize the aperture size, optical simulation using the finite-difference time-domain method was implemented. The optical simulation was performed with various aperture sizes from 0.3 μm to 1.1 μm and the optical power with the incidence angle as a function of the aperture size was evaluated. Based on the optical simulation results, the CMOS image sensor was designed and fabricated using 0.11 μm CMOS image sensor process. The effects of aperture size are investigated by comparison of the simulation and the measurement results.

This paper presents a CMOS image sensor with the in-pixel aperture technique for single-chip 2-D and 3-D imaging. In conventional image sensors, the aperture is located at the camera lens. However, in the proposed image sensor, the aperture is integrated on the CMOS image sensor chip and is formed at a metal layer of the CMOS image sensor (CIS) process. A pixel array of the image sensor is composed of the W, R, B, and PA pixels (W pixel with integrated metal aperture) for extracting color and depth information. While the image of the W pixel becomes blurred with increasing distance from a focused object, the image of the PA pixel maintains the sharpness. Therefore, the depth image can be obtained using the depth from the defocus method. The size of the pixel, which is based on a four-transistor active pixel sensor with pinned photodiode, is $2.8 \,\,\mu {\mathrm{ m}} \times 2.8\,\,\mu \text{m}$ . A prototype of the proposed image sensor was fabricated using the 0.11- $\mu \text{m}$ CIS process and its performance was evaluated.

We propose a linear-logarithmic CMOS image sensor with reduced fixed pattern noise (FPN). The proposed linear-logarithmic pixel based on a conventional 3-transistor active pixel sensor (APS) structure has additional circuits in which a photogate and a cascade MOSFET are integrated with the pixel structure in conjunction with the photodiode. To improve FPN, we applied the PMOSFET hard reset method as a reset transistor instead of NMOSFET reset normally used in APS. The proposed pixel has been designed and fabricated using 0.18-μm 1-poly 6-metal standard CMOS process. A 120 × 240 pixel array of test chip was divided into 2 different subsections with 60 × 240 sub-arrays, so that the proposed linear-logarithmic pixel with reduced FPN could be compared with the conventional linear-logarithmic pixel. We confirmed a reduction of pixel response variation which affected image quality.

A 3dimensional (3D) imaging is an important area which can be applied to face detection, gesture recognition, and 3D reconstruction. In this paper, extraction of depth information for 3D imaging using pixel aperture technique is presented. An active pixel sensor (APS) with in-pixel aperture has been developed for this purpose. In the conventional camera systems using a complementary metal-oxide-semiconductor (CMOS) image sensor, an aperture is located behind the camera lens. However, in our proposed camera system, the aperture implemented by metal layer of CMOS process is located on the White (W) pixel which means a pixel without any color filter on top of the pixel. 4 types of pixels including Red (R), Green (G), Blue (B), and White (W) pixels were used for pixel aperture technique. The RGB pixels produce a defocused image with blur, while W pixels produce a focused image. The focused image is used as a reference image to extract the depth information for 3D imaging. This image can be compared with the defocused image from RGB pixels. Therefore, depth information can be extracted by comparing defocused image with focused image using the depth from defocus (DFD) method. Size of the pixel for 4-tr APS is 2.8 μm × 2.8 μm and the pixel structure was designed and simulated based on 0.11 μm CMOS image sensor (CIS) process. Optical performances of the pixel aperture technique were evaluated using optical simulation with finite-difference time-domain (FDTD) method and electrical performances were evaluated using TCAD.

Lately, research on bolometer type uncooled infrared image sensor has been increasing for industrial applications. But it is hard to remove a Fixed Pattern Noise (FPN) of bolometer sensor. In this paper, a novel average-current calibration algorithm is presented for reducing bolometer resistance offset. A resistor which is produced standard CMOS process, on the average, has a deviation, respectively. We compensate for deviation of each active resistor using average-current calibration algorithm. The algorithm consists of as follows: bolometer pixel array, average current generator, current-to-voltage converters (IVCs), digital-to-analog converter (DAC), and analog-to-digital converters (ADCs). These bolometer-resistor array and readout circuit were designed and manufactured by 0.35μm standard CMOS process.