Li Gao

This letter proposes a novel single-port reflection-type phase shifter (SP-RTPS) based on the hybrid-integrated suspended line (HISL) technology. First, the topology and working principle of the SP-RTPS are proposed and analyzed theoretically. Unlike the conventional dual-port RTPS employing the branch-line/coupled-line coupler, the SP-RTPS comprises a rat-race coupler (RRC) with reflective loads to reflect the input signal back and output it at the same port with reconfigurable phase shift and invariant amplitude. Second, to miniaturize the size of conventional RRC, the SP-RTPS employs the $7\lambda $ /6-ring structure with open-stub loaded transmission lines (OSLTLs) to reduce the size by 65%. Finally, the SP-RTPS is designed, fabricated, and tested on the low-loss and self-packaged HISL technology at 2.45GHz. Measurement results show that the SP-RTPS provides a phase shift range (PSR) of 382° with a loss better than 1.47dB. Featuring full phase shift, high phase resolution, and low loss, the SP-RTPS is well-suited for reconfigurable reflectarrays (RRAs).

This letter presents a vector-sum phase shifter (VSPS) with low power and high gain based on a 28-nm bulk CMOS process. Informed by an analysis of the load characteristics of the quadrature all-pass filter (QAF), this circuit introduces and implements an innovative asymmetric-resonance structure. The improved QAF significantly reduces the quadrature amplitude error from 2 to 0.3 dB. Moreover, the circuit employs a current-reuse technique by cascading a 6-bit vector synthesis circuit with the common-source stage circuit at the DC level, effectively reducing DC power consumption while maintaining high gain. The proposed phase shifter (PS) realized a 1-dB bandwidth of 22–39 GHz (55.7% fractional bandwidth) and 360° phase shift with a phase resolution of 5.625°. The measured average gain is −1.5 dB, and the calculated corresponding root mean square (rms) gain and phase error are 0.37–0.64 dB and 0.32°–2.7°, respectively. The total DC power consumption is only 15 mW. This PS is particularly suitable for massive element phased-array beamforming, demonstrating over a 50% improvement in the figure of merit (FOM) compared to prior broadband designs.

This article presents a fully integrated all-in-one CMOS frequency management module (FMM) that features a direct-frequency-synthesis (DFS) architecture by fully integrating an LC-based reference of a temperature- and aging-stable frequency $f_{\text {LC}} =1024$ MHz and by directly operating the synthesizer at $f_{\text {LC}}$ . The FMM grants a $10\times $ wider loop bandwidth for over 20 dB of additional ring-oscillator (RO) noise suppression and supports fast frequency hopping with a settling time below $7~\mu $ s. Moreover, the FMM exploits the high-frequency sinusoidal reference with direct sampling, eliminating the need for a power-hungry divider and avoiding the division-ratio-squared in-band noise amplification, ultimately achieving an over 3-dB improved FoM_JIT. A 1.8-to-3.0-GHz frequency range with a 1-MHz channel step is achieved by employing a phase modulator for fractional-N frequency synthesis. Fabricated in 40-nm CMOS, the FMM consumes 13.5 mW and occupies an active area of 0.28 mm². The measured 18 FMM samples achieve a worst case frequency inaccuracy of −47/+42 ppm from −40 to $95~^{\circ } $ C, and after one week of accelerated aging at $150~^{\circ } $ C, the same samples exhibit −150/+70-ppm inaccuracy. The proposed FMM shows an rms jitter and spur of 932 fs and −53.6 dBc, respectively, with a fast frequency hopping that settles within $7~\mu $ s, representing a fully integrated FMM with state-of-the-art frequency inaccuracy and excellent frequency-hopping capabilities.

This article presents a frequency reconfigurable power amplifier (PA) for fifth-generation (5G) millimeter-wave dual-side local oscillator (LO) injection systems, which effectively reduces the LO design complexity. A tricoil transformer is proposed to design a high $Q$ broadband output matching network (OMN), thus enhancing power-efficiency at high-frequency band. Besides, two distinct reconfigurable resonator topologies are proposed for the design of both the input and interstage matching networks. These resonators effectively realize filtering functionality by utilizing the switch-off capacitance in conjunction with inductive resonance, while maintaining low-circuit losses. Importantly, this design methodology inherently embeds filtering capabilities within the matching network without introducing additional area overhead. The proposed PA is implemented in 28-nm bulk CMOS and realizes 18.4–20.2 dBm $P_{\text {sat}}$ , 13.7–19 dBm OP_1dB and 24.5%–34.7% PAE over n257–n261 bands. The PA exhibits maximum image/LO rejection (LOR) of 38.5/28.5 dBc. For 5G new radio (NR) frequency range 2 (FR2) 200 MHz 64-QAM signals (9.7 dB PAPR), the PA achieves average $P_{\text {out}}$ /PAE of >7.3 dBm and >5.2% with −25 dB EVM_rms over n257–n261. The PA occupies a core area of only 0.109 mm², making it suitable for cost-effective, high-yield 5G user equipment (UE) and large-scale phased-array applications.

This article presents a fully integrated D-band power amplifier (PA) with high output power and high efficiency, utilizing a two-way power combining technique and implemented in 28-nm bulk CMOS. An enhanced slow wave coplanar waveguide (ES-CPW) proposed in this article can achieve a higher phase constant and lower attenuation constant compared to conventional slow wave coplanar waveguides (S-CPWs), enabling simultaneous device miniaturization and performance enhancement. Based on this structure, a power combiner (PC) is designed to reduce the insertion loss while enhancing performance and minimizing the chip area, which achieves a 0.25-dB insertion loss with broadband operation and compact size. The PA measured results show a 3-dB bandwidth of 18.3 GHz from 122.3 to 140.6GHz. In addition, this PA can achieve a peak gain of 18.5dB, 16.2-dBm saturated output power (Psat), and a peak power-added efficiency (PAE) of 16.4% at 130 GHz. This allows the PA to achieve an average output power of 9.1 (6.5) dBm under 64-QAM (256QAM) modulation with a data rate of 45 Gb/s. To the best of the authors’ knowledge, the proposed PA realized the highest PAE, the widest power bandwidth (1-dB bandwidth), and the maximum data rate in CMOS technology and a similar operating band. Meanwhile, the total chip area is $0.32\times 0.31$ mm².

This article presents an up/down frequency converter (UDFC) supporting 5G frequency range 2 (FR2) communication applications. The design employs a wideband-intermediate frequency (IF) local oscillator (LO) reusable architecture with dual-side LO injection. The implemented UDFC utilizes a novel current-flipping-based mixer topology. Through the integration of a hybrid in-phase and quadrature generator (HIQG) and a reconfigurable IF polyphase filter (IF PPF), the design optimizes image rejection ratio (IRR) and enhances IF coverage, the design enables compatibility with both current sub-6-GHz communication devices and millimeter-wave (mmW) applications. Furthermore, a reconfigurable low-noise amplifier (LNA) is incorporated to further improve IRR in receiver (RX) mode. In addition, to meet the requirement of the signal dynamic range, a current-steering radio frequency variable gain amplifier (RF VGA) and a wideband IF VGA are employed to support wide gain tuning in TRX. Fabricated in a 40-nm CMOS technology, this design occupies a core area of 1.1 mm², achieving an IRR of 32–46.7/40.8–65.8dBc in transmit (TX)/RX modes with an IF coverage of 2.5–6.5GHz. In the TX mode, it operates over 24–30GHz in the low frequency band (LFB) and 37–43.5-GHz high frequency band (HFB), delivering a saturated output power of 17.6/17.2dBm and a peak power-added efficiency (PAE) of 18.7%/14.6% for LFB/HFB, respectively. In the RX mode, it covers 24–30GHz (LFB) and 37–41.5GHz (HFB), with a minimum noise figure (NF) of 6.4/7.1dB for LFB/HFB. A gain control range of >29dB is supported in both TX and RX modes. Compared with previous works, this UDFC exhibits significant advantages in IRR, IF bandwidth, and gain control range, making it an ideal solution for 5G communication applications such as handheld devices and virtual reality (VR) systems.

This paper presents a horizontally polarized (HP) omnidirectional filtering dielectric resonator (DR) antenna (DRA) and its circularly polarized (CP) counterpart, without extra filtering circuits. The HP filtering DRA comprises a DR and a single-layer circular substrate. A modified end-shorted Alford loop with center-shorted parasitic strips is positioned on the top of the substrate, two concentric circular slots are etched on the bottom. Wherein, the inner slot consists of four open stubs. This configuration excites three operating modes: the TE011+δ DR mode and two patch modes. Through mode cancellation between these modes, two radiation nulls are created near the passband, thus realizing filtering responses. The CP filtering design shares a highly similar structure with the HP one. The key difference lies in its bottom side, which features a single circular slot integrated with both open and shorted stubs. This setup enables filtering responses with left hand circular polarization (LHCP). Both the HP and CP filtering designs were fabricated and measured. The HP DRA features a measured -10-dB impedance bandwidth of 19% and a realized gain of 1.25 dBi within the passband. It has an electrical size of π×0.25²×0.19λ₀³. The CP design has an overlapped -10-dB impedance and 3-dB axial ratio (AR) bandwidth of 11.9%, with a realized gain of 0.7 dBic. Whereas, its electrical size increases to π×0.28²×0.18λ₀³. Both designs show omnidirectional radiation patterns with suppression levels over 19 dB and 13.3 dB, respectively.

This letter presents a 23–32/31–44 GHz reconfigurable dual-band variable gain amplifier (VGA) for 5G mm-wave transmitters. The design utilizes a constant phase structure with phase-compensation-circuits (PCCs) to minimize phase variation, while a high-impedance-ratio reconfigurable interstage matching network (ITMN) enables dual-band switching. To meet the requirement for high output power in mm-wave transmitters, load-pull is carried out to maximize the output 1 dB compression point (OP ${}_{1\text {dB}}$ ). Fabricated in TSMC 28-nm bulk CMOS process, the proposed VGA achieves a peak ${S} {_{21}}$ of 9.7/9.3 dB at 23–32/31–44 GHz with a gain tuning range of 18/16 dB. It delivers an OP ${}_{1\text {dB}}$ of 4.6/3.7 dBm at its maximum gain states. The rms phase error is below 0.9°/1.9°/0.4°/0.7° across 5G bands n258/n257/n260/n259. The circuit consumes 25.5 mW with a core size of 0.22 mm². With the aforementioned performance, the proposed VGA is highly competitive for 5G mm-wave mobile communication transmitters.