Hui-Yang Li

In this letter, we propose a method to design a quad-function filtering circuit using hybrid coaxial-dielectric resonators (DRs). The circuit features the combination of four circuit functions, which can be used to replace a filter, a single-pole double-throw (SPDT) switch, a power divider, and two balun circuits cascading in the radio frequency (RF) front-end system. A circuit model based on coupled resonators is introduced to combine the functions of an SPDT switch and a bandpass filter (BPF), where the switching of the passband is realized by controlling the admittances within the filter structure. Then, by using coaxial resonators, multiple feeding ports are simply arranged to the resonator to implement the circuit function of the power divider. Moreover, balanced-to-unbalanced signal conversion is enabled by utilizing the electromagnetic-field properties of the TM₀₁-mode DR without increasing the circuit complexity. Compared to conventional designs using cascaded circuits, the proposed circuit shows greatly reduced size and loss. For verification, a prototype circuit is fabricated and measured. Experimental results show good bandpass responses with a wide stopband (for filter), high common-mode (CM) suppression (for balun), accurate power division (for power divider), as well as low loss and high isolation (for SPDT switch).

This article presents a 24–30-GHz wideband transmit–receive (T/R) front-end module (FEM) for 5G millimeter-wave (mm-Wave) applications in the 150-nm GaN-on-SiC HEMT process. The power amplifier in the transmitting chain is constructed of two fully symmetrical push–pull amplifiers that are designed using transformer-based baluns. To improve efficiency, the harmonic control technique is used in the output impedance matching network, where the second-harmonic impedance can be optimized without affecting the fundamental response. A high-order stacked-transistor single-pole double-throw (SPDT) switch is designed with a low insertion loss of 0.75dB and a high input 1-dB compression point (IP ${}_{\mathrm {1dB}}$ ) of over 44dBm, ensuring almost no gain compression in transmitting mode. The low-noise amplifier (LNA) in the receiving chain is designed into a three-stage topology, achieving a flat gain and low-noise figure (NF) within the operating bandwidth. In measurements, the proposed FEM operating across 24–30 GHz demonstrates a maximum saturated power ( $P_{\mathrm {sat}}$ ) of 37.5dBm and peak power-added efficiency (PAE) of 32% in the transmitting mode. An error vector magnitude (EVM) of 5.75% and an average output power of 25.7 dBm with a 64-quadrature amplitude modulation (QAM) 5G FR2 modulated signal of 100-MHz bandwidth at 27 GHz are realized. In the receiving mode, the FEM demonstrates a NF of less than 3.1 dB, a flat small-signal gain of 20–21.3 dB, and an output 1-dB compression point (OP ${}_{\mathrm {1dB}}$ ) of 20.4 dBm.

This paper presents a broadband low-noise amplifier (LNA) monolithic microwave integrated circuit (MMIC) in 0.15-μm GaN-on-SiC technology. The LNA circuit is designed into a three-stage topology with three coupled-line structures. The first coupled-line structure is designed at the first stage for wideband input impedance matching and noise cancellation, while the second one is employed at the inter-stage to realize the g_m-boost for gain enhancement. Then, the last coupled-line structure forms a positive feedback signal paths from the drain to the gate of the output-stage transistor, which compensates the gain degradation at the high frequency band. With these three coupled-line structures, flat gain performance and low noise figure are achieved in a broadband frequency range. For demonstration, the LNA MMIC is fabricated. The measured results show a maximum gain of 22.6 dB at 27.6 GHz and a 3-dB bandwidth of 22.6 GHz from 7.2 to 29.8 GHz. The in-band noise figure is measured as 1.35-2.67 dB, while the output 1dB gain compression point (OP1dB) and output third-order intercept point (OIP3) are 20.9 dBm and 34.8 dBm at 28.5 GHz, respectively. The fabricated LNA has a compact die area of 2.64 mm² including all test pads.

In this article, we propose a method to design the dual-channel balanced-to-unbalanced (BTU) filtering power divider with equal and unequal division ratios. The whole circuit consists of one quad-mode dielectric resonator (DR), two single-mode DRs, and two coaxial resonators. By using these hybrid coaxial and DRs, the proposed design integrates two filtering channels into one circuit, where each channel contains functions of the balun, filter, and power divider, achieving high integration. The integration of the balun circuit function for balanced-to-unbalanced signal conversion is enabled by using electromagnetic-field properties of the two single-mode TM₀₁-mode DRs without increasing the circuit complexity. With two rotated L-shape metal probes as nonresonant nodes, the four modes of the quad-mode DR are divided into two sets and then separately coupled to the two single-mode DRs. The metal probe is loaded to each coaxial resonator to enable coupling between the coaxial resonator and quad-mode DR for the dual-channel circuit operation. Moreover, multiple feeding ports are simply arranged to the coaxial resonators to integrate the power divider function with equal and unequal power division ratios. Then, two channels of balanced-to-unbalanced filtering power dividers are realized in one circuit with high integration. For verification, design examples with equal and unequal power division ratios are provided. A 1:1:2 dual-channel filtering power divider is fabricated and measured with a high common-mode (CM) suppression, good bandpass responses, an accurate power division ratio, and high isolation between two-circuit channels.

In this paper, we propose a compact wideband on-chip millimeter-wave (mm-wave) reconfigurable wideband filtering switch in 28-nm bulk CMOS technology. A dual-mode LC resonator loaded with transistors is used to achieve wideband filtering responses with a transmission zero at the lower frequency band. The resonant frequency of the resonator and the location of the transmission zero can be conveniently tuned to reconfigure the passband and stopband frequencies by turning on and off the transistor. Moreover, the passband can also be switched on and off, enabling the single-pole single-throw filtering switch circuit function. In this way, the proposed mm-wave reconfigurable filtering switch is applicable to the integrated sensing and communication (ISAC) system, where image rejection in communication operation and a wide bandwidth (or high resolution) in sensing operation are both required. Furthermore, to meet the applications in the ISAC systems with different architectures, extension designs of the proposed reconfigurable filtering switch with the impedance conversion function, high-order responses, balanced-to-unbalanced transition, and differential input/output ports are presented in detailed. For demonstration, the wideband reconfigurable filtering switch has been fabricated. The core circuit has a very compact size of 0.205 $\times$ 0.140 mm $^{2}$ . Experimental results show that the passband can be reconfigured between 20-55 GHz and 37-44 GHz, with a rejection $>$ 17 dB for sensing operation and $>$ 12 dB image-band rejection for communication operation, respectively. High off-state isolation of better than 24.8 dB is also achieved.

This article presents a reconfigurable dual-band low noise amplifier (LNA) for 5G millimeter-wave (mmWave) applications in the TSMC 28-nm bulk CMOS process. The reconfigurable LNA is based on a two-stage amplifier design with switchable triple-coupled transformer and capacitor technologies applied to the inter-stage and output matching networks. The switchable triple-coupled transformer can change the self-inductance of the transformer coils by tuning the magnetic flux entering the coils. To suppress the image frequency interference, magnetic–electric hybrid coupling is integrated into the inter-stage matching network, which introduces a transmission zero, resulting in a high image rejection ratio. The measured result shows that the low band has a peak gain of 18.1 dB with a 3-dB bandwidth of 23.8–33.5 GHz, and the high band has a peak gain of 18.9 dB with a 3-dB bandwidth of 34.4–41.4 GHz. The image rejection ratio is better than 32.7 dBc with an intermediate frequency of 8 GHz. The measured NF is better than 3.5 dB at both bands. The IP1dB is $-$ 19 to $-$ 15.1/ $-$ 18.5 to $-$ 15.2 dBm in the low/high band. The fabricated LNA has a very compact core size of 0.09 mm $^{2}$ , and the total power consumption is only 14 mW.

This letter presents a 23–42.5-GHz Ka -band ultrawideband (UWB) variable gain amplifier (VGA) for 5G applications, realized in TSMC 28-nm bulk CMOS process. The proposed VGA adopts a three-level transistor stack structure, and additional inductors are added to compensate for pole roll-off at high frequencies. A cross-connected gain control structure is used to reduce phase variation by minimizing the impedance variation caused by gain tuning. The proposed UWB VGA has a measured peak gain of 9.6 dB at 26 GHz with a 3-dB bandwidth of 23–42.5 GHz. The measured gain tuning range is 16 dB and the root-mean-square (rms) phase variation is smaller than 2 $^{\circ}$ . The UWB VGA draws 15-mA current from 1.8-V power supply with a core size of 0.21 mm $^{2}$ .

This paper presents a three-stage wideband LNA with gain switching technique designed for 5G millimeter-wave applications operating at 23.6-46.5 GHz. By deriving an analytical equation of input impedance and noise matching, a two-pole matching network based on ladder transformer is introduced. The coupling between the transformers can be used to control the two poles of S $_{11}$ and simultaneously match the source impedance to the optimized noise impedance, achieving broadband input matching and low noise figure (NF). A 24 dB gain tuning range with 6 dB per step has been designed to accommodate different input power level for automatic gain control (AGC). The gain control is implemented with current slicing at the 2 $^{\mathrm{nd}}$ and 3 $^{\mathrm{rd}}$ stages, which can keep input/output impedance nearly constant during gain switching. The proposed wideband LNA has been fabricated in 28-nm bulk CMOS process with a chip size of only 0.13 mm $^{2}$ . Measured results show a peak gain of 23 dB within a 3-dB bandwidth from 23.6 to 46.5 GHz, with S $_{11}$ better than $-$ 10 dB over the bandwidth. The measured NF is 2.2 -3.7 dB with an average of 3 dB. The input 1 dB gain compression point (IP1dB) ranges from $-$ 27 to $-$ 23.8 dBm throughout the gain bandwidth. Moreover, the measured gain can be switched with value of 21.5/14.9/9.1/2.9/ $-$ 3 dB, and the corresponding NF and IP1dB are 3.7/4.9/7.9/12.8/14.3 dB and $-$ 23.8/ $-$ 19.5/ $-$ 14.8/ $-$ 13.1/ $-$ 8.8 dBm at 33 GHz, respectively. This design is suitable for wideband 5G millimeter-wave communication.