Rongzheng Ding

Complementary FET (CFET) technology is attracting widespread interest as one of the most promising scaling boosters. The additional interconnect layer required for the bottom device in CFET results in a more complex distribution of parasitic capacitance. In this article, we propose a strategy to extract the parasitic capacitance of CFET in standard cell (SDC). Considering the unique multilayer structure of CFET and the practical requirements for circuit design, the interconnections between gates can be categorized into five distinct configurations. Each configuration is further divided into three styles. The capacitance associated with the fixed-style part remains unchanged regardless of design variations and should be included in the compact model of the transistor. Each style is modeled using analytical approaches. For the first time, we evaluate the parasitic capacitance between the interconnections of PFET and NFET in CFET. The comparison between the model and numerical field solver simulation results, along with the transient simulation results obtained by applying the proposed strategy to circuits, comprehensively validates both the feasibility of the strategy and the accuracy of the model.

A physics-based compact model is developed for ultra-scaled gate-all-around field-effect transistors (GAAFETs), addressing increasingly prominent physical effects: quantum confinement, quasi-ballistic transport, and short channel effects (SCEs). The model employs approximate analytical solutions to the fundamental physical equations, mimicking true device physics while maintaining computational efficiency. In addition to predicting terminal characteristics, it accurately computes subband energies, quantum centroid, quasi-ballistic transmission coefficient, and electrostatic scaling length. Through these internal physical quantities, the model serves not merely as a concise representation of device behaviors but also reveals fundamental physical insights. The model’s verified consistency with TCAD simulations and experimental data confirms its accuracy across a wide range of bias conditions and GAAFET dimensions, while also highlighting the physical mechanisms captured by the model for leading-edge technology nodes.

At cryogenic temperatures, carrier mobility in bulk silicon exhibits a significantly different temperature dependence compared with that at room temperature. To capture this difference and accurately calculate cryogenic carrier mobility in technology computer-aided design (TCAD) simulation, we have developed a physics-based analytical mobility model. The proposed model is built upon two components: ionized impurity scattering and neutral impurity scattering. The ionized impurity scattering component is developed within the unified Klaassen’s mobility model framework, which also incorporates other scattering mechanisms such as lattice scattering and carrier–carrier scattering. To overcome the limitations of Klaassen’s model below 100 K, we incorporated the nonlinear screening effect and used the variable phase approach (VPA), a robust method for calculating minority impurity mobility. The neutral impurity scattering component adopts an existing practical model, which accurately captures the effect of scattering by neutral impurities at low temperatures. Our model exhibits good match to the experimental data on both majority and minority carrier mobility. Above 100 K, our model can be simplified to the original Klaassen’s mobility model, demonstrating its compatibility with the existing models at higher temperatures. In cryogenic bulk silicon simulations, our model exhibits good convergence performance and accuracy, making it applicable in cryogenic device simulations.

In this article, we evaluate various crystal orientation configurations for silicon ultrascaled nanosheet FETs (NSFETs) to explore the optimum combination of wafer surface and channel orientations. The increasingly prominent physical phenomena, including quantum confinement and quasi-ballistic transport, are captured physically by advanced simulation methodology. The carrier density profile and transport-related parameters exhibit a strong dependence on the crystallographic orientations of the channel and the wafer directions. The quantum confinement effects are least pronounced in the n-type NSFETs with a (100) surface, and the p-type NSFETs with a (110) surface. The $ \langle \text{100} \rangle$ and $ \langle \text{111} \rangle$ channel orientations demonstrate the largest ballistic injection velocity for electrons and holes, respectively. Uniaxial stress technology, as an efficient performance booster, may further improve the transport properties, but the enhancement may saturate at high stress level. In the ballistic limit, we predict that the homo-oriented CMOS inverter of $\text{(}\text{110}\text{)}/\langle \text{111} \rangle$ configuration has a more balanced N/P current, and the hetero-oriented CMOS inverter, comprising a 5 ${\times}$ 10 nm n-type NSFET of $\text{(}\text{100}\text{)}/\langle \text{100} \rangle$ and a 5 ${\times}$ 10 nm p-type NSFET of $\text{(}\text{110}\text{)}/\langle \text{111} \rangle$ , will yield a speed enhancement exceeding 20% when compared with the prevailing industry standard of the $\text{(}\text{100}\text{)}/\langle \text{110} \rangle$ configuration.

This letter reports a study on statistical variability of random dipole fluctuation-induced variation (DFV) in gate-all-around (GAA) nanosheet devices that adopt the interface dipole engineering technique for V _t modulation, a new intrinsic device variability source that has yet been reported. The impact of DFV with the incorporation of La and Al is characterized by threshold voltage standard deviations (σ V_t ), which are 3.7–8.2 mV and 7.7–17.2 mV for the dipole-induced potential shifts of 100–500 meV in the calibrated NFET and PFET devices, respectively. DFV follows the Pelgrom law. When device shrinks, σ V_t due to DFV will increase inversely proportional to the square root of channel area. Furthermore, as a new source of variability, DFV is compared with metal grain granularity (MGG), random dopant fluctuation (RDF), and oxide thickness variation (OTV) using the statistical impedance field method (sIFM) simulation technique. The results show that DFV contributes 10% (NFET) and 25% (PFET) to the overall variation when the dipole-induced potential shifts are set at 300 meV, indicating that DFV is a significant contributor to device variability with importance second only to MGG.

This article proposes a novel zigzag-cell design for the six-transistor static random access memory (SRAM) bitcell in the complementary field-effect transistor (CFET) framework. The zigzag-cell design not only maintains the aggressive area reduction but also allows for shorter bitlines, directly benefiting from the circuit layout changes caused by the CFET architecture. The specific layouts of the zigzag-cell design are introduced by incorporating them into two process flows with different complexity. The first assumed process flow contains only the essential steps of CFET SRAM, and according to which the zigzag-cell bitcell can achieve an area reduction of more than 20% over the thin-cell bitcell. Moreover, the performance of zigzag-cell SRAM is also improved by 4.6% and 16.3% in read time and write margin, respectively. Following the second more complicated process flow, the zigzag-cell design does not offer further area reduction compared with the thin-cell design, but it needs fewer metal layers. The proposed design is a promising choice for the CFET SRAM bitcell layout.

We propose a new technology and design platform using combined common gate (CG) N/PFET complementary field-effect transistor (CFET) as basic element for CMOS circuit applications. Two CFET unit structures, namely, CG and N-gate (NG), are identified to form base design elements. Through the two units, all circuit logic functions in standard cell library and SRAM can be realized without significant process complication. A multigradient neural network (MNN)-based SPICE compact modeling methodology is developed for these CFET units. As an example, MNN model generation is illustrated for CG with the output matching well with the TCAD data within and beyond the range of model extraction. Circuit simulations are exercised using the MNN models and demonstrated successfully the expected circuit functionalities. As the CFET technology be adopted as mainstream in future, this novel design framework proposed would enable efficient logic design.

Threshold voltage ( ${V_{t}}$ ) engineering is critical and challenging in the advanced logic devices. Inducing interface dipoles by the incorporation of dopants into the gate dielectrics is an emerging scheme to modulate the threshold voltage. However, the impact of those dipoles on gate-stack performance is of great concern. In this work, we present the first-principles calculations of dielectric constant and tunneling current of high- ${k}$ gate-stack with lanthanum (La) dopants. It is found that incorporation of La improves the local dielectric constant as well as the equivalent oxide thickness (EOT), but degrades the gate leakage current. The calculated results are consistent with the reported experimental data. Furthermore, by analyzing the transmission coefficients and band alignment across the gate-stack, a theoretical explanation for the change of gate leakage current is provided.

The complementary field-effect transistor (CFET) with stacked N-type FET (NFET) and P-type FET (PFET) is an attractive approach to shrink the footprint of multiple devices at circuit level and increase transistor density. Compared with traditional device structure, the unique geometry of CFET brings very different parasitics. In this work, we take the inverter as an exemplar CFET circuit building block and provide analytical compact models of calculating parasitic capacitance, which is critical to enable fast and accurate simulations at circuit level. The validity of the models is calibrated and verified with 3-D numerical simulations. A comparison between the CFET inverter with its same ground-rule gate-all-around FET (GAAFET) counterpart reveals the critical CFET design parameters and demonstrates performance advantage of CFET architecture.