Yusi Zhao

Complementary FET (CFET) technology is attracting widespread interest as one of the most promising scaling boosters. The additional interconnect layer required for the bottom device in CFET results in a more complex distribution of parasitic capacitance. In this article, we propose a strategy to extract the parasitic capacitance of CFET in standard cell (SDC). Considering the unique multilayer structure of CFET and the practical requirements for circuit design, the interconnections between gates can be categorized into five distinct configurations. Each configuration is further divided into three styles. The capacitance associated with the fixed-style part remains unchanged regardless of design variations and should be included in the compact model of the transistor. Each style is modeled using analytical approaches. For the first time, we evaluate the parasitic capacitance between the interconnections of PFET and NFET in CFET. The comparison between the model and numerical field solver simulation results, along with the transient simulation results obtained by applying the proposed strategy to circuits, comprehensively validates both the feasibility of the strategy and the accuracy of the model.

A physics-based compact model is developed for ultra-scaled gate-all-around field-effect transistors (GAAFETs), addressing increasingly prominent physical effects: quantum confinement, quasi-ballistic transport, and short channel effects (SCEs). The model employs approximate analytical solutions to the fundamental physical equations, mimicking true device physics while maintaining computational efficiency. In addition to predicting terminal characteristics, it accurately computes subband energies, quantum centroid, quasi-ballistic transmission coefficient, and electrostatic scaling length. Through these internal physical quantities, the model serves not merely as a concise representation of device behaviors but also reveals fundamental physical insights. The model’s verified consistency with TCAD simulations and experimental data confirms its accuracy across a wide range of bias conditions and GAAFET dimensions, while also highlighting the physical mechanisms captured by the model for leading-edge technology nodes.

In this article, we evaluate various crystal orientation configurations for silicon ultrascaled nanosheet FETs (NSFETs) to explore the optimum combination of wafer surface and channel orientations. The increasingly prominent physical phenomena, including quantum confinement and quasi-ballistic transport, are captured physically by advanced simulation methodology. The carrier density profile and transport-related parameters exhibit a strong dependence on the crystallographic orientations of the channel and the wafer directions. The quantum confinement effects are least pronounced in the n-type NSFETs with a (100) surface, and the p-type NSFETs with a (110) surface. The $ \langle \text{100} \rangle$ and $ \langle \text{111} \rangle$ channel orientations demonstrate the largest ballistic injection velocity for electrons and holes, respectively. Uniaxial stress technology, as an efficient performance booster, may further improve the transport properties, but the enhancement may saturate at high stress level. In the ballistic limit, we predict that the homo-oriented CMOS inverter of $\text{(}\text{110}\text{)}/\langle \text{111} \rangle$ configuration has a more balanced N/P current, and the hetero-oriented CMOS inverter, comprising a 5 ${\times}$ 10 nm n-type NSFET of $\text{(}\text{100}\text{)}/\langle \text{100} \rangle$ and a 5 ${\times}$ 10 nm p-type NSFET of $\text{(}\text{110}\text{)}/\langle \text{111} \rangle$ , will yield a speed enhancement exceeding 20% when compared with the prevailing industry standard of the $\text{(}\text{100}\text{)}/\langle \text{110} \rangle$ configuration.

This letter reports a study on statistical variability of random dipole fluctuation-induced variation (DFV) in gate-all-around (GAA) nanosheet devices that adopt the interface dipole engineering technique for V _t modulation, a new intrinsic device variability source that has yet been reported. The impact of DFV with the incorporation of La and Al is characterized by threshold voltage standard deviations (σ V_t ), which are 3.7–8.2 mV and 7.7–17.2 mV for the dipole-induced potential shifts of 100–500 meV in the calibrated NFET and PFET devices, respectively. DFV follows the Pelgrom law. When device shrinks, σ V_t due to DFV will increase inversely proportional to the square root of channel area. Furthermore, as a new source of variability, DFV is compared with metal grain granularity (MGG), random dopant fluctuation (RDF), and oxide thickness variation (OTV) using the statistical impedance field method (sIFM) simulation technique. The results show that DFV contributes 10% (NFET) and 25% (PFET) to the overall variation when the dipole-induced potential shifts are set at 300 meV, indicating that DFV is a significant contributor to device variability with importance second only to MGG.