Kenichi Okada

This article presents a time-modulated variable-gain amplifier (VGA) employing a clock-sampling topology governed by a duty-cycle control (DCC) loop. By modulating the effective operation time of the amplifier rather than altering its RF bias conditions, for precise tuning of the clock duty cycle, enabling phase consistency at millimeter-wave frequencies. The proposed DCC loop provides precise and stable DCC, enabling robust time-domain gain modulation and mitigating phase perturbations typically associated with conventional VGA architectures. Implemented in 65-nm CMOS technology, the VGA consumes 4.9–103 mW from a 1-V supply, depending on the gain setting, and occupies a core area of $1150\times 280~\mu $ m. Measurements demonstrate a 30-dB continuous gain-control range with a 3-dB bandwidth from 24 to 30 GHz and a peak gain of 29.6 dB at 28 GHz. Across 24–29.7 GHz, the measured rms phase error ranges from 0.01° to 0.18° between the highest and lowest gain modes, validating the phase stability of the proposed approach. In addition, an output 1-dB (OP1dB) compression point of 12.5dBm is achieved, indicating robust large-signal performance. The proposed time-modulated VGA is well-suited for scalable millimeter-wave phased-array systems requiring wide-range gain control with minimal phase distortion.

This article presents a Ka-band phased-array multiple-input multiple-output (MIMO) receiver for sixth-generation (6G) wireless networks. A time-division (TD) MIMO architecture is combined with DP antenna array to support eight MIMO streams in the Ka band. The complex weights of each RF element in both polarization arrays are sequentially switched at the Nyquist rate to enable fast-stream switching for MIMO stream coexistence. The TD approach achieves full phased-array reuse and delivers high array gain and spatial selectivity for each stream at the expense of generating switching harmonics. To address this issue, a non-uniform time-hopping (TH) sequence is introduced in this article to spectrally spread the switching harmonics and mitigate the direct blocker folding. A proof-of-concept phased-array receiver is fabricated in 65-nm CMOS, integrating eight RF elements in a 7.2-mm² core area and consuming 335.2 mW. Combined with DP antennas, the phased-array receiver supports $4 \times 4$ TD-MIMO across both polarizations and achieves a maximum data rate of 38.4Gb/s using eight 800-MHz 64-QAM signals in over-the-air (OTA) measurements. Benefiting from the TD-MIMO architecture, the phased-array receiver achieves 0.078 mm² and 5.23 mW per element per stream. With the proposed non-uniform TH (NUTH) dithering, deep notches are generated at switching harmonics and 42.9-dB alias suppression is achieved. The proposed phased-array receiver also demonstrates a 34-dB improvement in blocker tolerance, maintaining –30-dB EVM_rms under a 0-dBc in-band blocker sweeping across –90° to 90° field of view (FoV) in MIMO OTA measurements.

This article presents a 256-element CMOS active phased-array transmitter (TX) that works at 19 GHz for low-Earth orbit (LEO) satellite applications. This work proposes a 90° coupler-end structure for circular polarization (CP) wave generation, which features low power consumption and enables dual-CP waves emitting in two directions. In addition, this work employs two calibration techniques to improve cross-polarization discrimination (XPD) in single-CP and dual-CP modes. The power consumption of the proposed structure is 9.4 W at 56-dBm average effective isotropic radiated power (EIRP), which is 40% lower than the state-of-the-art. It consumes 17.8 W at 64.7-dBm maximum EIRP. The beam-steering ability of this work can achieve ±65° with a sidelobe level <10-dBc. For the EVM measurement result, in single-CP mode, this work can support 256 amplitude-phase shift keying (APSK) modulation with a 2-Gbaud symbol rate on a 56-dBm EIRP output. In dual-CP mode, this work can support 256 APSK modulation with a 250-MBaud symbol rate on a 56-dBm EIRP output.

This work presents a D-band high-power-density four-element phased-array transceiver for 6G user equipment (UE). Conventional designs require large multi-stage LO generation circuits for D-band up/down conversion, making it difficult to achieve compact size and low-power consumption. To address this, we propose an integrated LO chain using an injection-locked tripling phase shifter (ILTPS), which enables both frequency tripling and phase shifting within a single circuit without multi-stage amplifiers. The ILTPS achieves an area of 0.088 mm² and a power consumption of 15 mW. In addition, to realize high power density, the transceiver integrates a bi-active sub-harmonic mixer (BA-SHM) and a D-band PA/LNA with PA-sharing TDD switching. An eight-element antenna-in-package (AiP) module using two transceiver ICs operates in the 142–164-GHz frequency range, achieving an EIRP of 25.7 dBm and a maximum data rate of 56 Gbps. The power consumption per element is 150 mW in TX mode and 93 mW in RX mode with 1 V VDD. The active area of this transceiver is 8.5 mm², and it is implemented using a 65 nm CMOS process.

This article presents a stacked-PCB-based broadband D-band horn antenna with high efficiency fabricated using a conventional PCB process. By replacing the conventional multilayered PCB with multiple stacked single-layer PCBs, the dielectric material inside the horn aperture is removed, and the antenna walls can be formed using vertically aligned through-holes. This architecture enables flexible stacking, allowing the aperture size to be scaled simply by adjusting the number of layers, which in turn scales the antenna gain. These modifications also lead to improved antenna characteristics, including gain and radiation pattern. The measured reflection coefficient remains below −18 dB across the entire D-band (110–170 GHz). The sidelobe is less than −10 dB and cross-polarization discrimination is lower than −30 dB. The gain is measured to be 19.8 $\pm$ 1.7 dB.

This article presents a 300-GHz-band amplifier-last outphasing phased-array transmitter with path mismatch calibration in a 65-nm CMOS technology. Calibration is essential for mitigating impairments in outphasing systems used for wideband communication. The transmitter integrates two independent sub-THz LO generation chains to calibrate the phase mismatch between two paths and configure the phase delay between different phased-array elements. An integrated RF outphasing amplifier calibrates the amplitude mismatch and improves the transmitter’s effective isotropic radiated power (EIRP). After calibration, the transmitter exhibits a 3.3-dB improvement in error vector magnitude and supports 16 QAM modulation at 52 Gb/s over a distance of 9 cm. It achieves a peak EIRP of 8.9 dBm at 246 GHz, with a minimum EIRP of 5.0 dBm across the frequency range from 237 to 250 GHz. An 8×1 phased-array transmitter is implemented, demonstrating a main lobe scanning range of ±12° in the $E$ -plane.

This paper introduces a testbed for joint radar-communication (JRC) utilizing frequency-division multiplexing (FDM) in the D-band (116–170 GHz). It employs a wideband 65 nm CMOS transceiver, originally designed for high-throughput communications. Utilizing external frequency-modulated continuous-wave (FMCW) chirps, it achieves a range resolution of 13.6mm and sub-millimeter accuracy in radar-only mode. In simultaneous JRC operation, it sustains a 24mm range resolution while supporting data rates up to 20 Gb/s using 16-QAM and 32-QAM modulation schemes. A single-transmitter, single-receiver (1T1R) configuration is used to demonstrate radar and communication coexistence within a shared spectrum, whereas an extended single-transmitter, two-receiver (1T2R) setup validates the simultaneous demodulation of both direct and reflected links, demonstrating multi-user capabilities. Doppler measurements are used to verify low-speed velocity sensing via segmented acquisition, illustrating how factors such as distance, radar cross section (RCS), and beam alignment together impact signal-to-noise ratio (SNR), radar visibility, and the quality of the communication link. This system-level validation marks the first experimental proof of a communication-focused architecture in the D-band, establishing the feasibility of scaling existing CMOS hardware for future integrated system-on-chip (SoC) solutions capable of simultaneous high-speed communication and fine-resolution sensing.