A 9-GHz Digital Fractional-N PLL With Dynamic-Threshold DTC
- 1 January 2026
- journal article
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Solid-State Circuits Letters
- Vol. 9, 250-253
Abstract
No abstract availableFunding Information
- Japan Science and Technology Agency (JST) as part of Adopting Sustainable Partnerships for Innovative Research Ecosystem (JPMJAP2514)
- JST-Research and Development Program for Next-Generation Edge Artificial Intelligence (AI) Semiconductors (JPMJES2515)
- Very Large Scale Integration (VLSI) Design and Education Center (VDEC) in collaboration with Cadence Design Systems, Inc., Synopsys, Inc., Mentor Graphics, Inc., and Keysight Technologies Japan, Ltd.
This publication has 11 references indexed in Scilit:
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- A 0.65-to-1V-V DD 10.5-to-11.85GHz Fractional-N Sampling PLL Achieving 71.47fs Integrated Jitter and <-60dBc Near-Integer Fractional Spur in 40nm CMOS2026
- 12.1 A 74fs-Jitter, -59dBc-Spur Fractional-N DPLL Using a Supply-Resilient Time-Amplifying Dual-Ramp DTC2026
- A 6.65-to-7.75GHz Fractional-N Digital PLL with Analog Pre-Distortion DTC Implementing 2nd/3rd-Order Calibration and Achieving −65.7dBc Fractional Spur and 154fs Integrated Jitter2025
- A PVT-Robust 5.5GHz Fractional-N Cascaded RO-Based Digital PLL with Voltage-Domain Feedforward Noise Cancellation2025
- 34.1 A 65fsrms-Jitter and -272dB-FoMjitter,N 10.1GHz Fractional-N Digital PLL with a Quantization-Error-Compensating BBPD and an Orthogonal-Polynomial LMS Calibration2025
- A Low-Jitter Fractional- N Digital PLL Adopting a Reverse-Concavity Variable-Slope DTCIEEE Journal of Solid-State Circuits, 2024
- A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs2022
- A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCOIEEE Journal of Solid-State Circuits, 2021
- 17.3 A −58dBc-Worst-Fractional-Spur and −234dB-FoMjitter, 5.5GHz Ring-DCO-Based Fractional-N DPLL Using a Time-Invariant-Probability Modulator, Generating a Nonlinearity-Robust DTC-Control Word2020