Andreia Cathelin

This article presents a broadband 5G power amplifier (PA) robust to voltage standing wave ratio (VSWR) variations and featuring high efficiency up to deep power back-off (PBO) in 28-nm FD-SOI CMOS technology. The proposed architecture, based on a quasi-balanced structure and an inductive load, offers an alternative to the conventional Doherty PA to maintain its $\text {PAE}_{\text {6dBPBO}}$ enhancement up to 3:1 VSWR over a wide bandwidth. A detailed theoretical analysis demonstrates the improved broadband performance that can be achieved with this architecture, as well as its robustness to VSWR variations. Indeed, the degradation of its $\text {PAE}_{\text {6dBPBO}}$ is kept below 7% between 22 and 44GHz. The circuit achieves 24% $\text {PAE}_{\text {6dBPBO}}$ and 16% $\text {PAE}_{9.\text {7dBPBO}}$ at 28GHz, while guaranteeing linearity in line with the 5G standard. The PA occupies a surface area of 0.82 mm².

For the past few decades, extensive work has been done to realize RF integrated communication circuits at THz (100–1000-GHz) frequencies. However, for silicon-based devices, which are the most commercially accessible, our circuits fail to produce meaningful output power beyond a few hundred GHz, and as the frequency and bandwidth increase, the effects of noise and phase noise become more and more prominent. Until recently, communication systems above $f_{\max }/2$ have been struggling to reach highly complex (16QAM and above) modulation schemes largely due to difficulties inherent to achieving phase coherency and high SNR. The system presented herein uses a Kramers–Kronig transmitter, which suggests the ability to reconstruct the signal’s phase by only measuring amplitude. We showcase an integrated transmitter that achieves phase coherency using fully on-chip free-running oscillators above $f_{\max }/2$ . By pursuing this style of wireless communications, future works may potentially be able to realize phase-encoded fully integrated systems without off-chip sources or exceedingly difficult PLLs. By reaching high-order QAM schemes, transmitter data rates above 200-GHz carrier have the opportunity to rapidly increase with respect to the current state-of-the-art.

A fully integrated wideband THz autodyne frequency-modulated continuous-wave (FMCW) radar is reported in this work. The core of the transmitter is a five-stage voltage-controlled ring oscillator (VCRO). Wideband operation is achieved through the radiation of the fifth harmonic (5f_o) of the proposed VCRO. Additionally, an on-chip folded slot antenna is designed for radiation and reception of voltage-controlled oscillator (VCO)’s signal while providing the optimum matching condition at 5f_o. The radar is fabricated in a 55-nm BiCMOS process using only CMOS transistors with f_T/f_max = 255/290 GHz. The radar achieves a peak equivalent-isotropically radiated power (EIRP) of 6.2 dBm using a hyper-hemispherical silicon lens and a 57 GHz bandwidth with an in-band power variation of 5.8 dB. It consumes 152 mW of dc power and occupies an area of 0.16 mm². The autodyne radar topology utilizes the oscillator transistors as the mixing element, generating an intermediate frequency (IF) signal that is extracted from the V_DD line. Simulation results of the autodyne operation and IF generation mechanism are provided, verifying the dual operation of VCO as a transmitter and receiver. At last, the radar is tested in a focal imaging setup to take images of human teeth and capture the cavities and root canals inside the teeth. To the best of our knowledge, this radar achieves the highest bandwidth and smallest area among the VCO-based CMOS radars in the 100–500 GHz range.

Considering the power-hungry nature of speech processing, a keyword spotting (KWS) unit, used to detect multiple spoken words, is often integrated as a front-end layer. KWS systems are always active, and thus, it is extremely important to optimize the devoted power budget. In this context, this article presents a programmable low-power event-driven real-time spectrogram extraction unit tested for the KWS application. This chip, fabricated in 28-nm FD-SOI CMOS technology, has been combined with a software-defined convolutional neural network to demonstrate the recognition of 11 audio classes (ten keywords $+$ background $+$ unknown) with an accuracy equal to 87.9% and an activity-dependent power consumption measured at 391.6 nW, for a 12-keyword/min average speech rate.

This paper proposes a design-oriented DC model for MOS transistors in advanced nanometric technologies, based on only six parameters. The proposed model is based on the inversion charge and includes the main short-channel effects for accurately describing the behavior of the transistor DC drain current in all regions (linear to saturation) and regimes of operation (weak to strong inversion). The proposed model is critically compared to existing inversion charge-based models, highlighting the main limitations of previous models presented in the literature and the advantages and disadvantages of our proposal. Then, regarding the model implementation, previously presented inversion charge-based models require a numerical solver to link the transistor’s DC current to its DC node voltages. In this work, we propose an innovative approach to model implementation via the analytical approximation of the Lambert function’s principal branch. Thanks to this approximation, the proposed design-oriented model offers for the first time an analytical single-piece expression of the drain current as an explicit function of the transistor node voltages. The validity of both the proposed transistor DC model and its analytical single-piece implementation is confirmed through simulation and measurement results, using the industrial productionlevel model UTSOI2 as a reference. The evaluations were conducted on MOS transistors with lengths of 30 nm, 60 nm, and 150 nm in STMicroelectronics 28 nm FD-SOI CMOS technology, to validate our results in minimum length, intermediate length, and long transistors in the selected technology. The proposed model achieves an average error of less than 6% in drain current evaluation compared to industry-standard models such as UTSOI2, while significantly reducing computational complexity.

This paper presents a novel charge-based MOSFET model, denoted ACM2, including velocity saturation and drain-induced barrier lowering. Employing the proposed model, all the DC characteristics (currents and charges) and the small-signal equations can be expressed as single-piece expressions valid in all inversion (weak, moderate, and strong) regions. When applied to bulk technology, ACM2 has 5 DC parameters, and an extra parameter is included for SOI technologies to account for back gate bias. Straightforward procedures are provided for extracting the short-channel parameters associated with velocity saturation and back gate bias. Experimental results demonstrate that the DC and small-signal characteristics of the ACM2 model match the silicon measurements in bulk and SOI technologies, with typical errors of less than 20 % in the DC currents and 30 % in the transconductances. The validity of the model is further verified with two design examples. Firstly, simulations of a CMOS inverter in a 130 nm bulk technology show similar results using the PSP or ACM2 models. Then, an RF design example is provided. The ACM2 model is employed to design a 2.4 GHz low-noise-amplifier in a 28 nm FD-SOI CMOS technology. Obtained results in terms of S ₁₁ , S ₂₁ , NF, and IIP3 are consistent with simulations using the complete UTSOI2 model provided in the technology design kit.

The integration of Single-Photon Avalanche Diodes (SPADs) in CMOS Fully Depleted Silicon-On-Insulator (FD-SOI) technology under a buried oxide (BOX) layer and a silicon film containing transistors makes it possible to realize a 3D SPAD at the chip level. In our study, a nanostructurated layer created by an optimized arrangement of Shallow Trench Isolation (STI) above the photosensitive zone generates constructive interferences and consequently an increase in the light sensitivity in the frontside illumination. A simulation methodology is presented that couples electrical and optical data in order to optimize the STI trenches (size and period) and to estimate the Photon Detection Probability (PDP) gain. Then, a test chip was designed, manufactured, and characterized, demonstrating the PDP improvement due to the STI nanostructuring while maintaining a comparable Dark Count Rate (DCR).

This article presents four twisted hybrid couplers exhibiting low insertion losses for 5G applications. Thanks to an accurate pre-sizing methodology and an electromagnetic model, three different twisted hybrid coupler architectures are presented and compared to offer different form factor trade-offs while maintaining state-of-the-art performances. A 26–44-GHz multi-band 90 $^{\circ}$ twisted hybrid coupler exhibiting low insertion losses is then presented to improve its inherent bandwidth. Using a tunable 3-bit slow-wave architecture, the hybrid coupler offers eight operating modes allowing it to select the desired center frequency and covers a bandwidth of more than 51 $\%$ while minimizing its losses. The hybrid coupler achieves insertion losses lower than 2.2 dB with a minimum of 1.45 dB at 26 GHz and a phase shift between the two output paths of 95 $^{\circ}$ $\pm$ 5 $^{\circ}$ . The coupler is highly robust to process variations, and offers a high power handling up to 35 dBm input. All of these circuits are implemented in a CMOS 28 nm FD-SOI process.

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