Claude Thibeault

As the demand for low‐power electronic products grows, asynchronous circuits are considered a good alternative for addressing power consumption issues. Applying dynamic voltage scaling (DVS) in asynchronous circuits can further improve their power efficiency. However, asynchronous circuits face challenges, such as performance analysis considering voltage, temperature, and process variations. This paper proposes a new statistical performance analysis model for asynchronous pipelines. This model can be applied to two different styles of asynchronous circuits. The results show that this model has reasonable accuracy on estimated mean delay (2% error on average) compared to detailed analysis carried out with low‐level Monte Carlo (MC) circuit simulations.

Due to commercial pressures, North-American printed circuit-board assembly manufacturers have had to reposition themselves in the more difficult market segment of lower volume, higher complexity products, also called high-mix, low-volume (HMLV). The high per-unit costs of these products justify substantial diagnosis and repair efforts when defects are detected in production. Although automated diagnostics is desirable, the low production volumes impose severe limits on available data. We propose a novel approach based on knowledge modeling and case-based reasoning for automated diagnosis of assembled printed circuit boards in an HMLV production environment. Our hybrid approach can overcome the knowledge-acquisition bottleneck even in a data-poor environment. The proposed approach does not require contributions from product designers or experts and is designed to operate using only information available during manufacturing. Our test results show that our diagnostic system can detect, locate and classify all single faults and multiple faults affecting up to three neighboring nodes with a better success rate than the reference commercial tool. Moreover, case base data, including board layout information and user feedback from previous repairs, is used to feed a recommender system to provide repair suggestions. A production and repair data simulator is described and used to evaluate the recommender system’s effectiveness.

Classical transition delay fault (TDF) model-based delay tests cannot detect small-delay defects (SDDs) properly in many circuits because they do not set the test slack properly to match the size of the tested delay fault. In this article, we propose a new method of using faster-than-at-speed clocks to enhance a classical TDF-based test pattern set and create an optimized SDD test that can detect effective SDDs. We define effective SDDs as SDDs that can immediately fail a circuit and distinguish them from those that grow over time to fail the circuit (reliability defects). The optimized SDD test developed in this article can either target only effective SDDs or also include reliability defects that are close to fail a circuit. In order to improve the SDD test quality, the proposed optimization method uses the recently proposed weighted slack percentage (WeSPer) as the SDD test quality metric to match each pattern with an appropriate test clock speed and then generates the proper masking vector. The optimization method includes a technique for reducing the final pattern count while keeping WeSPer value high. On a set of benchmark circuits, the proposed technique is able to improve the WeSPer value by up to 32.97% (a relative improvement of 60.98%) compared to classical at-speed testing using the same pattern set. This article also discusses the application of this technique on a self-timed circuit that has previously been at-speed tested. The proposed optimization technique improved the SDD test quality from 60% to 69% for preexisting set of test clocks and patterns. Post-silicon test results for the processor are included in this article.

In this paper, we analyze the impact of the power supply noise and the power distribution network (PDN) impedance variation on the timing margin in both modes for ICs with multiple clock domains. We investigate the so-called intermodulation products (IMPs). We show that IMPs are mainly induced by the dependent nature of the transistors. We also provide experimental results showing that scan-based delay testing can be optimistic with respect to the mission mode for maximum achievable nominal frequency prediction, even at lower clock frequencies. We also show that IMPs can induce timing margin fluctuations that can be larger than that of the ones induced by the voltage droop in the test mode. Using an improved HSpice simulation model of a PDN validated by experimental results, we also quantify the timing margin variation due to power noise in the test mode as a function of the clock frequency, including the so-called clock stretching phenomenon. Finally, we propose a robust test signal scheme for multiple clock domain chips. The simulation results reveal that this scheme is less sensitive to PDN impedance variation than that of the most popular existing test schemes, and that it provides timing margins closer to those obtained in the mission mode.

Polar codes are a recently proposed class of block codes that provably achieve the capacity of various communication channels. They received a lot of attention as they can do so with low-complexity encoding and decoding algorithms, and they have an explicit construction. Their recent inclusion in a 5G communication standard will only spur more research. However, only a couple of ASICs featuring decoders for polar codes were fabricated, and none of them implements a list-based decoding algorithm. In this paper, we present ASIC measurement results for a fabricated 28 nm CMOS chip that implements two different decoders: the first decoder is tailored toward error-correction performance and flexibility. It supports any code rate as well as three different decoding algorithms: successive cancellation (SC), SC flip and SC list (SCL). The flexible decoder can also decode both non-systematic and systematic polar codes. The second decoder targets speed and energy efficiency. We present measurement results for the first silicon-proven SCL decoder, where its coded throughput is shown to be of 306.8 Mbps with a latency of 3.34 us and an energy per bit of 418.3 pJ/bit at a clock frequency of 721 MHz for a supply of 1.3 V. The energy per bit drops down to 178.1 pJ/bit with a more modest clock frequency of 308 MHz, lower throughput of 130.9 Mbps and a reduced supply voltage of 0.9 V. For the other two operating modes, the energy per bit is shown to be of approximately 95 pJ/bit. The less flexible high-throughput unrolled decoder can achieve a coded throughput of 9.2 Gbps and a latency of 628 ns for a measured energy per bit of 1.15 pJ/bit at 451 MHz.

BACKGROUND: Airline carriers have equipment, procedures, and protocols in place to handle in-flight medical events (IFMEs). Community physicians may be asked for aid during IFMEs. Cross-Sectional Survey of Physicians on Providing Volunteer Care for In-Flight Medical Events surveyed self-assessed awareness and knowledge, perceived barriers, and suggestions for improving responses to IFMEs.METHODS: We composed a survey regarding clinicians’ self-assessed understanding of in-flight resources, procedures, flight environmental issues, and Good Samaritan protections. The survey was distributed primarily via electronic mail to medical staff list serves to a total of approximately 1300 physicians representing 2 health networks that serve urban, suburban, and rural areas in both inpatient and outpatient settings.RESULTS: Total number of responses was 418. Physician response rate was 29.2% (379/1300). In 3% (39/1300), the responder either failed to indicate their background or was another type of health care professional (e.g., dentist, medical student, physician assistant). Of the physicians, 37.5% (142/379) were primary care and 42% (177/418) of responders reported at least one experience of being asked to volunteer. When asked how well they understand the protocols with which medical events are handled, 64% (262/412) responded “not at all” and 23% (94/412) reported “a little” knowledge. Only 56% (223/397) answered that 75% or more of U.S. flights have ground medical support available. There were 73% (298/411) who believed airlines were required to have medical supplies, but 54% (222/410) reported no knowledge of supplies available. A total of 69% (279/403) believed or were sure that the U.S. has a Good Samaritan law that applies to IFMEs.DISCUSSION: Many physicians lack basic knowledge about IFMEs. Responders may assist more effectively if better informed about protocols and the availability of ground medical support. Education and timely information support are recommended.Chatfield E, Bond WF, McCay B, Thibeault C, Alves PM, Squillante M, Timpe J, Cook CJ, Bertino RE. Cross-Sectional Survey of Physicians on Providing Volunteer Care for In-Flight Medical Events. Aerosp Med Hum Perform. 2017; 88(9):876–879.

Polar codes are a new class of block codes with an explicit construction that provably achieve the capacity of various communications channels, even with the low-complexity successive-cancellation (SC) decoding algorithm. Yet, the more complex successive-cancellation list (SCL) decoding algorithm is gathering more attention lately as it significantly improves the error-correction performance of short- to moderate-length polar codes, especially when they are concatenated with a cyclic redundancy check code. However, as SCL decoding explores several decoding paths, existing hardware implementations tend to be significantly slower than SC-based decoders. In this paper, we show how the unrolling technique, which has already been used in the context of SC decoding, can be adapted to SCL decoding yielding a multi-Gbps SCL-based polar decoder with an error-correction performance that is competitive when compared to an LDPC code of similar length and rate. Post-place-and-route ASIC results for 28 nm CMOS are provided showing that this decoder can sustain a throughput greater than 10 Gbps at 468 MHz with an energy efficiency of 7.25 pJ/bit.

Polar codes are a new class of block codes with an explicit construction that provably achieve the capacity of various communications channels, even with the low-complexity successive-cancellation (SC) decoding algorithm. Yet, the more complex successive-cancellation list (SCL) decoding algorithm is gathering more attention lately as it significantly improves the error-correction performance of short-to moderate-length polar codes, especially when they are concatenated with a cyclic redundancy check code. However, as SCL decoding explores several decoding paths, existing hardware implementations tend to be significantly slower than SC-based decoders. In this paper, we show how the unrolling technique, which has already been used in the context of SC decoding, can be adapted to SCL decoding yielding a multi-Gbps SCL-based polar decoder with an error-correction performance that is competitive when compared to an LDPC code of similar length and rate. Post-place-and-route ASIC results for 28 nm CMOS are provided showing that this decoder can sustain a throughput greater than 10 Gbps at 468 MHz with an energy efficiency of 7.25 pJ/bit.

In this work, we present a family of architectures for polar decoders using a reduced-complexity successive-cancellation decoding algorithm that employs unrolling to achieve extremely high throughput values while retaining moderate implementation complexity. The resulting fully-unrolled, deeply-pipelined architecture is capable of achieving a coded throughput in excess of 1 Tbps on a 65 nm ASIC at 500 MHz---three orders of magnitude greater than current state-of-the-art polar decoders. However, unrolled decoders are built for a specific, fixed code. Therefore we also present a new method to enable the use of multiple code lengths and rates in a fully-unrolled polar decoder architecture. This method leads to a length- and rate-flexible decoder while retaining the very high speed typical to unrolled decoders. The resulting decoders can decode a master polar code of a given rate and length, and several shorter codes of different rates and lengths. We present results for two versions of a multi-mode decoder supporting eight and ten different polar codes, respectively. Both are capable of a peak throughput of 25.6 Gbps. For each decoder, the energy efficiency for the longest supported polar code is shown to be of 14.8 pJ/bit at 250 MHz and of 8.8 pJ/bit at 500 MHz.