Alessandro Girardi

This study presents an acoustic emission (AE) monitoring strategy based on MEMS (Micro- Electro-Mechanical Systems) sensors applied to 3D-printed structures. AE data were analyzed using the b-value method to track damage development and Natural Time (NT) analysis to identify the onset of critical conditions. A comparison with a commercial piezoelectric sensor revealed similar performance, with both sensors detecting a reduction in the b-value preceding failure. MEMS sensors demonstrated an enhanced capacity to capture high-frequency signals. These results underline the potential of MEMS sensors as cost-effective tools for structural health monitoring in additive manufacturing contexts.

Editor’s notes: This article investigates how voltage-dependent resistor nonlinearity degrades harmonic distortion in active-RC continuous-time sigma–delta modulators. Results show that larger resistor silicon area effectively mitigates this effect across supply voltages from 5 to 1.2 V. —José Augusto Nacif, Federal University of Viçosa, Brazil —Omar Paranaiba Vilela Neto, Federal University of Minas Gerais (UFMG), Brazil

The sigma-delta converter is a very precise analog-to-digital converter (ADC) and consists of two main blocks: the modulator and the digital decimation filter. It achieves high resolution by oversampling and noise shaping, which removes the noise from the desired band. Digital decimation filters are then used to reduce the output data rate of the modulator close to the Nyquist rate and at the same time filter the high frequency noise generated by the modulator or present at the input. There are numerous papers in the literature comparing numerous topologies of sigma-delta modulators in different manufacturing technologies. However, the same is not true for decimator filters, for which there are much fewer papers describing and comparing topologies in detail for an integrated circuit implementation. Therefore, the main objective of this work is to present a guideline for the design of an optimized digital decimation filter for sigma-delta ACDs with physical synthesis results in a 65 nm CMOS process. A 3rd order sigma-delta modulator with 24 kHz bandwidth and 128 of oversampling, targeting the audio band, was chosen as inputdata for the filter. This modulator was modeled and simulated in the Matlab/Simulink environment and achieved an effectivenumber of bits (ENOB) of 17.91 bits. The optimized process target to reduce power and area of the filter while maintainingthe ENOB of this modulator at the output of the ADC.

This paper presents the design, simulation, prototyping, and measurement results of a digitally tunable fourth order Gm-C low-pass filter (LPF) for multi-standard radio receivers. The LPF cut-off frequency can be tunned by digitally selecting the transconductance of the basic reconfigurable operational transconductance amplifiers (OTAs) that compose the circuit. Four operation modes allow for control of the OTA transconductances and, consequently, the scaling of power consumption. The filter was designed and prototyped in a 1.8 V 180 nm CMOS process. The measurement results indicate that the configurability provides a cutoff frequency of 1.90/3.56/6.07/8.15 MHz with a power consumption ranging from 9.9 to 13.1 mW. The designed filter achieves an IIP3 of 8.17 dBm for a signal bandwidth of 8.15 MHz. The performance, in terms of power dissipation, noise, and cut-off frequency, is at the same order of magnitude compared to recent related works reported in the literature. The advantages are a compact area, small sensitivity to component mismatches, and low design complexity. The proposed filter presents electrical characteristics suitable for the application in radio receivers for multi-carrier WCDMA signals.

Photovoltaic (PV) cells are being adopted as a viable and cost-effective option for implementing receivers within Visible Light Communication (VLC) systems, primarily in indoor environments. Accurately estimating the generated current and voltage of the PV cell based on incident light is crucial when designing VLC systems.For this assessment, the 1D2R electrical equivalent model, which incorporates a diode and two resistors, is employed.In AC small signal analysis, the diode is substituted by its dynamic counterpart, which comprises a dynamic resistance in parallel with an equivalent capacitance. This study introduces an approach to measure and characterize the small-signal parameters of a PV cell operating at the maximum power point (MPP), open circuit (OC), and short circuit (SC) bias points. This is achieved through a closed-loop frequency response system, calibrated to encompass illuminance levels ranging from 50 to 500 lux.The procedure for estimating the AC response of the PV cell is outlined, and the outcomes are subsequently employed in an analytical parameter extraction methodology. Experimental results from a 20 x 40 mm PV cell reveal that MPP represents the least favorable bias point in terms of bandwidth, whereas the SC bias point exhibits the most favorable performance. This observation validates the hypothesis that the optimal bias point for energy harvesting in PV cells is the worst bias point for communication purposes.

This article describes a design optimization method based on variable conversion applied to low-voltage (LV) CMOS analog integrated circuits. For supply voltages in the range of 0.3 to 0.6 V, traditional design variables (e.g., transistor channel width $W$ and $\text {gm}/I_{D}$ ) are not suitable for exploring the design space, leading to impractical design solutions. We show that it is more efficient to convert the design variables into current $I_{D}$ and channel length $L$ , since these parameters are directly related to circuit performance for LV applications. The proposed optimization algorithm explores the design space to obtain solutions that satisfy the design constraints while analyzing the effects of process, voltage, and temperature variations (PVT). We apply the proposed method for design optimization in terms of area and power consumption of a fourth-order LV active filter preceded by a programmable gain amplifier (PGA), in 130 nm CMOS technology. A fully differential 0.6 V operational amplifier (OTA) is designed as a building block and used in the filter in a bottom-up approach. Measurements of a prototype chip validate the proposed method and resulted in a 0.784 mW, 0.066 mm2 active low-pass filter with a cutoff frequency of 2.5 MHz and attenuation that meet the requirements of the IEEE 802.15.4 technical standard for 2.4 GHz receivers.

In this paper, a new low-power and low-voltage configurable-gain small-signal amplifier is proposed. It is based on an active negative resistance circuit and incorporates an improved technique for controlling output common-mode voltage stability in all gain range using a replica bias strategy. The circuit modeling and sizing procedure are described, as well as a prototype version in 180-nm CMOS process for operation with a supply voltage of 0.4 V. The measurement results demonstrate the ability to provide variable gain from 3 to 22 dB for a unity gain frequency of 55 kHz with power consumption in the range of 94 to 549 nW. The performance is comparable to that of state-of-the-art low-voltage variable-gain amplifiers, with the advantage of requiring less silicon area.

Machine failure in modern industry leads to lost production and reduced competitiveness. Maintenance costs represent between 15% and 60% of the manufacturing cost of the final product, and in heavy industry, these costs can be as high as 50% of the total production cost. Predictive maintenance is an efficient technique to avoid unexpected maintenance stops during production in industry. Vibration measurement is the main non-invasive method for locating and predicting faults in rotating machine components. This paper reviews the techniques and tools used to collect and analyze vibration data, as well as the methods used to interpret and diagnose faults in rotating machinery. The main steps of this technique are discussed, including data acquisition, data transmission, signal processing, and fault detection. Predictive maintenance through vibration analysis is a key strategy for cost reduction and a mandatory application in modern industry.

Most mobile and wearable devices present digital audio signal processing capabilities. Since the nature of audio signals is analog, there is a need to use analog-to-digital converters (ADCs) with high-resolution for a high signal-to-noise ratio audio acquisition. This paper presents the high-level modeling and design of a continuous-time third-order sigma-delta modulator (CT-SDM) with an FIR DAC for audio devices, using a supply voltage of 0.5 V. The design is divided in three steps and is carried out using the Delta-sigma toolbox and a discrete-time to continuous-time (DT-CT) transformation. First, the schematic implementation with verilogA models is done to estimate the first-integrator amplifier specifications for the modulator to provide 14 bits of ENOB. Following, a two-stage inverter-based amplifier is designed and used to verify the design strategy. Finally, a transistor-level implementation of OTAs and comparator is done to evaluate the CT-SDM performance. An in-depth analysis and discussion are presented to explain the achieved results with those transistor-level circuits.