Ben Kaczer

The 22nm fully-depleted silicon-on-insulator (FDSOI) technology is considered near-ideal for creating low-power cryogenic control electronics, a key milestone in the pursuit of large-scale fault-tolerant quantum computers. However, it is essential to assess the device reliability under conditions of interest, as various gate stack reliability phenomena such as bias temperature instability (BTI) and hot carrier degradation (HCD) have been reported active at 4K. This study comprehensively analyzes the shift in device parameters induced by BTI stress and recovery from room temperature down to 4K. A new method of assessing the impact of cryogenic BTI on ultra-low-power applications is presented, showcasing how nMOS devices of the 22nm technology prove to be ready for long-term cryo-operation, whereas pMOS devices do not.

We apply our finite element-based framework, introduced in Part 1, to understand the effects of channel thickness and doping on the degradation of indium–gallium–zinc oxide (IGZO)-based thin-film transistors (TFTs) with different architectures. By taking into account only experimentally extracted band alignments and amorphous semiconductor-specific physics, it is possible to explain apparent discrepancies in previously reported positive bias temperature instabilities (PBTI) trends. Our analysis shows that common PBTI benchmarks used in standard inversion-mode bulk Si devices cannot be employed in thin-film accumulation-mode IGZO devices. Finally, based on these insights, we propose device optimization strategies to reduce the electron trapping component of PBTI in amorphous IGZO TFTs.

We present a finite-element-based 1-D formalism to solve the Poisson equation for a thin-film transistor with a floating body. We apply our framework to InGaZnO (IGZO)-based devices, taking into account its subgap density of states (DoS), revealing its impact on device electrostatics, which is fundamental for predicting device performance and reliability. Our simple 1-D approach yields identical results as the more computationally intensive 2-D TCAD implementations, and it enables the convenient implementation of physics-based IGZO-specific models. Finally, we apply the new framework to quantify the IGZO deep subgap DoS measured by light-assisted $I$ – $V$ spectroscopy.

We propose an extended version of the design technology co-optimization (DTCO) flow, which—in contrast to the commonly acknowledged DTCO paradigm relying on the power–performance–area (PPA) metric—considers reliability as a tangible parameter, thereby leading to a concept of PPAR (“R” stands for “reliability”). As a demonstration of this concept, we carry out a comprehensive reliability analysis of future imec nanosheet field-effect-transistor (NSFET) logic nodes with gate lengths scaling from 15 to $10{\,}$ nm. Our focus is placed on hot-carrier degradation (HCD) and bias temperature instability (BTI) modeling over stress time of up to ten years. For an accurate description of HCD, we employ our technology computer-aided design (TCAD)-based HCD model, which relies on the modeling of carrier transport. A thorough analysis of the electric field and carrier concentration shows that both quantities peak at the rounded nanosheet (NS) corners, which enhances HCD; the most severe HCD occurs in NSFETs with the smallest corner radii. BTI simulations—conducted with the nonradiative multiphonon (NMP) model—exhibit a similar behavior: BTI becomes stronger as the NS corners become sharper. Overall, all degradation metrics decrease monotonically as the NS corner radius increases. These results indicate that field-effect transistor (FET) architectures with larger NS corner radii provide improved robustness against both HCD and BTI, and should be favored for future technology nodes. Our concept allows considering the reliability of future (not yet fabricated) transistor nodes, thereby making reliability an essential DTCO ingredient.

We present imecSHE, a 3-D deterministic Boltzmann transport equation (BTE) solver for computing heat generation in realistic devices. Input-power-scaled Gaussian heat-generation profiles are shown to overestimate heating in the nanosheet-FET (NSFET) by an order of magnitude. Our simulations resolve the 3-D topology of heat generation and show that lowering the carrier effective mass can significantly reduce heating. Mobility-inferred effective mass is further employed to qualitatively study the channel reorientation effect on heat generation. Along the imec roadmap A14 $\rightarrow $ A3 scaling, p-FETs benefit the most with the heat-fraction (HF) dropping from 0.76% to 0.32%, while the n-FET HF is nearly unchanged. Finally, scaling studies identify actionable levers. Shorter channels and smaller drain size reduce heat. By providing physics-based heat-generation profiles in realistic 3-D devices instead of assumed heat sources, imecSHE enables quantitative optimization of device and process design to suppress heat generation for technology pathfinding.

investigate the origin of negative threshold voltage shifts in back-gated amorphous IGZO TFTs under positive bias and high temperature stress. Combined DC and 1/f noise measurements reveal that the stress does not generate new dielectric traps but instead broadens the IGZO conduction band tail states. A recovery experiment confirms that the associated threshold voltage, subthreshold swing, and noise degradation are reversible. Simulations using an in-house Poisson solver confirm the experimental observations that high-temperature stress increases hydrogen doping and the density of sub-gap states.

Ring-oscillator (RO) circuits have historically been used to characterize the performance of CMOS technologies, as they can easily expose both process variability and aging through a straightforward circuit structure. ROs are widely employed to study degradation mechanisms such as bias temperature instability (BTI) and hot carrier degradation (HCD), which progressively deteriorate circuit performance over time. Consequently, accurate characterization of CMOS variability at both the device and circuit levels is essential for precise end-of-life prediction of the integrated circuits (ICs). In this context, this article presents a novel IC design that enables the statistical characterization of both process variability and aging phenomena in ROs. Our chip design contains hundreds of ROs, distributed across six electrically isolated modules or subarrays fabricated in a $1 \times 1$ mm die area. Each module provides high testing versatility, allowing individual access to each RO designed in five different threshold-voltage flavors, as well as ROs designed with thick-oxide IO transistors. Each module consists of a fully functional array, equipped with Force-and-Sense biasing and an on-chip heater structure to enable testing at elevated temperatures up to $325~^{\circ } $ C. This design has been implemented in a commercially available 0.9 V, 28 nm HKMG CMOS technology.