Dimosthenis Masouros
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Research Subjects
Dimosthenis Masouros has a total of 33 co-authors. Here are the top co-authors by number of shared publications:
- Dimitrios Soudris
National Technical University of Athens
25 shared publications - Sotirios Xydis
National Technical University of Athens
17 shared publications - Achilleas Tzenetopoulos
National Technical University of Athens, Athens, Greece
7 shared publications - Aggelos Ferikoglou
National Technical University of Athens, Athens, Attica, Greece
6 shared publications - Andreas Kosmas Kakolyris
ETH Zurich, Zurich, Switzerland
3 shared publications - Christos Sad
Electronics Laboratory, Physics Department, Aristotle University of Thessaloniki, 54124 Thessaloniki, Greece
3 shared publications
Latest Publications
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Parallel and Distributed Systems
- Vol. 37 (11) , 2570-2586
FLEX : Flexible Federated Learning With Asynchronous Peer-to-Peer Communication and Adaptive Aggregation
- 1 November 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Parallel and Distributed Systems
- Vol. 37 (11) , 2570-2586
FLEX : Flexible Federated Learning With Asynchronous Peer-to-Peer Communication and Adaptive Aggregation
- Open Access
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
MALIWAN: Performance and Energy Efficiency Co-Optimization of GEMM on Versal ACAP Architectures
- 26 July 2026
- Published by Association for Computing Machinery (ACM)
- p. 1-7
Open AccessMALIWAN: Performance and Energy Efficiency Co-Optimization of GEMM on Versal ACAP Architectures
- 1 July 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 75 (7) , 2290-2304
$\Omega$Ωkypous: Harnessing Timing Slacks and Coordinated DVFS for Power-Efficient Serverless Workflows
- 1 July 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Computers
- Vol. 75 (7) , 2290-2304
$\Omega$Ωkypous: Harnessing Timing Slacks and Coordinated DVFS for Power-Efficient Serverless Workflows
- Open Access
- 14 April 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Embedded Computing Systems
- Vol. 25 (3) , 1-30
SynergAI: Edge-to-Cloud Synergy for Architecture-Driven High-Performance Orchestration
The rapid evolution of Artificial Intelligence (AI) and Machine Learning (ML) has significantly heightened computational demands, particularly for inference-serving workloads. While traditional cloud-based deployments offer scalability, they face challenges such as network congestion, high energy consumption, and privacy concerns. In contrast, edge computing provides low-latency and sustainable alternatives but is constrained by limited computational resources. In this work, we introduce SynergAI , a novel framework designed for performance- and architecture-aware inference serving across heterogeneous edge-to-cloud infrastructures. Built upon a comprehensive performance characterization of modern inference engines, SynergAI integrates a combination of offline and online decision-making policies to deliver intelligent, lightweight, and architecture-aware scheduling. By dynamically allocating workloads across diverse hardware architectures, it effectively minimizes Quality of Service (QoS) violations. We implement SynergAI within a Kubernetes-based ecosystem and evaluate its efficiency. Our results demonstrate that architecture-driven inference serving enables optimized and architecture-aware deployments on emerging hardware platforms, achieving an average reduction of 2.4× in QoS violations compared to a State-of-the-Art (SotA) solution.
- 14 April 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Embedded Computing Systems
- Vol. 25 (3) , 1-30
Open AccessSynergAI: Edge-to-Cloud Synergy for Architecture-Driven High-Performance Orchestration
The rapid evolution of Artificial Intelligence (AI) and Machine Learning (ML) has significantly heightened computational demands, particularly for inference-serving workloads. While traditional cloud-based deployments offer scalability, they face challenges such as network congestion, high energy consumption, and privacy concerns. In contrast, edge computing provides low-latency and sustainable alternatives but is constrained by limited computational resources. In this work, we introduce SynergAI , a novel framework designed for performance- and architecture-aware inference serving across heterogeneous edge-to-cloud infrastructures. Built upon a comprehensive performance characterization of modern inference engines, SynergAI integrates a combination of offline and online decision-making policies to deliver intelligent, lightweight, and architecture-aware scheduling. By dynamically allocating workloads across diverse hardware architectures, it effectively minimizes Quality of Service (QoS) violations. We implement SynergAI within a Kubernetes-based ecosystem and evaluate its efficiency. Our results demonstrate that architecture-driven inference serving enables optimized and architecture-aware deployments on emerging hardware platforms, achieving an average reduction of 2.4× in QoS violations compared to a State-of-the-Art (SotA) solution.
- Open Access
- 24 March 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
- Vol. 23 (1) , 1-27
GNΩSIS: Lessons Learned in Generating a High-Level Synthesis Dataset
High-Level Synthesis (HLS) streamlines FPGA programming by abstracting low-level hardware complexities, facilitating rapid microarchitecture customization through the use of directives. However, identifying optimal directives remains a significant challenge, particularly for software developers without extensive hardware expertise. HLS-driven Design Space Exploration (DSE) addresses this challenge by automating the generation of directive configurations through a variety of techniques. The effectiveness of these methods heavily relies on the quality of the data on which they are built. Unfortunately, existing datasets are often constrained in scope, complexity, and device diversity. To address these limitations, we present GNΩSIS, 1 the largest open-source HLS dataset, to the best of our knowledge, containing almost 219K design points generated from prominent benchmark suites and public repositories. The dataset covers two FPGAs with varying resource characteristics and three clock frequencies. Additionally, we introduce a versatile framework to automate design point generation. We evaluate the impact of frequency scaling, FPGA architecture, and optimization targets on Quality of Result (QoR) metrics, analyze HLS directive effectiveness across code constructs, and study design transferability across FPGAs and frequencies. These analyses provide practical insights into QoR and HLS behavior, offering guidance for designers with limited optimization experience. We believe GNΩSIS will enhance FPGA accessibility and act as an enabler for innovation in HLS-driven DSE research. The dataset is publicly accessible on Hugging Face, 2 and the framework is available on GitHub. 3
- 24 March 2026
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Architecture and Code Optimization
- Vol. 23 (1) , 1-27
Open AccessGNΩSIS: Lessons Learned in Generating a High-Level Synthesis Dataset
High-Level Synthesis (HLS) streamlines FPGA programming by abstracting low-level hardware complexities, facilitating rapid microarchitecture customization through the use of directives. However, identifying optimal directives remains a significant challenge, particularly for software developers without extensive hardware expertise. HLS-driven Design Space Exploration (DSE) addresses this challenge by automating the generation of directive configurations through a variety of techniques. The effectiveness of these methods heavily relies on the quality of the data on which they are built. Unfortunately, existing datasets are often constrained in scope, complexity, and device diversity. To address these limitations, we present GNΩSIS, 1 the largest open-source HLS dataset, to the best of our knowledge, containing almost 219K design points generated from prominent benchmark suites and public repositories. The dataset covers two FPGAs with varying resource characteristics and three clock frequencies. Additionally, we introduce a versatile framework to automate design point generation. We evaluate the impact of frequency scaling, FPGA architecture, and optimization targets on Quality of Result (QoR) metrics, analyze HLS directive effectiveness across code constructs, and study design transferability across FPGAs and frequencies. These analyses provide practical insights into QoR and HLS behavior, offering guidance for designers with limited optimization experience. We believe GNΩSIS will enhance FPGA accessibility and act as an enabler for innovation in HLS-driven DSE research. The dataset is publicly accessible on Hugging Face, 2 and the framework is available on GitHub. 3
- Open Access
- 30 March 2025
- Published by Association for Computing Machinery (ACM)
- p. 26-32
Leveraging DVFS for Energy-Efficient and QoS-aware Edge Video Analytics
- 30 March 2025
- Published by Association for Computing Machinery (ACM)
- p. 26-32
Open AccessLeveraging DVFS for Energy-Efficient and QoS-aware Edge Video Analytics
- Open Access
- 30 March 2025
- Published by Association for Computing Machinery (ACM)
- p. 15-21
Towards Elastic Memory Allocation of Serverless Functions in Disaggregated Memory Systems
- 30 March 2025
- Published by Association for Computing Machinery (ACM)
- p. 15-21
Open AccessTowards Elastic Memory Allocation of Serverless Functions in Disaggregated Memory Systems
- Open Access
- 30 March 2025
- Published by Association for Computing Machinery (ACM)
- p. 261-268
Towards Asynchronous Peer-to-Peer Federated Learning for Heterogeneous Systems
- 30 March 2025
- Published by Association for Computing Machinery (ACM)
- p. 261-268
Open AccessTowards Asynchronous Peer-to-Peer Federated Learning for Heterogeneous Systems
- Open Access
- 25 December 2024
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Reconfigurable Technology and Systems
- Vol. 18 (1) , 1-32
CollectiveHLS: A Collaborative Approach to High-Level Synthesis Design Optimization
High-Level Synthesis (HLS) has played a pivotal role in making FPGAs accessible to a broader audience by facilitating high-level device programming and rapid microarchitecture customization through the use of directives. However, manually selecting the right directives can be a formidable challenge for programmers lacking a hardware background. This article presents CollectiveHLS, an ultra-fast, knowledge-driven approach to optimizing HLS designs. It automates the identification and application of optimal directive configurations from the original source code, focusing on minimizing design latency and ensuring synthesizability. This optimization approach is entirely data-driven, offering a generalized HLS tuning solution without reliance on Quality of Result (QoR) models or meta-heuristics. CollectiveHLS is designed, implemented, and evaluated using around 60 applications sourced from well-established benchmark suites and GitHub repositories, all running on a Xilinx UltraScale + MPSoC ZCU104. It achieves an average geometric mean speedup of up to \(23.1\times\) compared to the official source code without directives, while maintaining synthesizability and feasibility rates of 100% and 96.6%, respectively, matching those of Vitis, the industry-standard framework for FPGA acceleration. Comparisons with resource over-provisioning, traditional genetic algorithm-based Design Space Exploration (DSE), and State-of-the-Art (SotA) approaches demonstrate that CollectiveHLS produces designs of comparable quality \(14.6\times\) faster on average. These results underscore the potential of our approach as an ultra-fast and automated solution for HLS optimization.- 25 December 2024
- Published by Association for Computing Machinery (ACM) in ACM Transactions on Reconfigurable Technology and Systems
- Vol. 18 (1) , 1-32
Open AccessCollectiveHLS: A Collaborative Approach to High-Level Synthesis Design Optimization
High-Level Synthesis (HLS) has played a pivotal role in making FPGAs accessible to a broader audience by facilitating high-level device programming and rapid microarchitecture customization through the use of directives. However, manually selecting the right directives can be a formidable challenge for programmers lacking a hardware background. This article presents CollectiveHLS, an ultra-fast, knowledge-driven approach to optimizing HLS designs. It automates the identification and application of optimal directive configurations from the original source code, focusing on minimizing design latency and ensuring synthesizability. This optimization approach is entirely data-driven, offering a generalized HLS tuning solution without reliance on Quality of Result (QoR) models or meta-heuristics. CollectiveHLS is designed, implemented, and evaluated using around 60 applications sourced from well-established benchmark suites and GitHub repositories, all running on a Xilinx UltraScale + MPSoC ZCU104. It achieves an average geometric mean speedup of up to \(23.1\times\) compared to the official source code without directives, while maintaining synthesizability and feasibility rates of 100% and 96.6%, respectively, matching those of Vitis, the industry-standard framework for FPGA acceleration. Comparisons with resource over-provisioning, traditional genetic algorithm-based Design Space Exploration (DSE), and State-of-the-Art (SotA) approaches demonstrate that CollectiveHLS produces designs of comparable quality \(14.6\times\) faster on average. These results underscore the potential of our approach as an ultra-fast and automated solution for HLS optimization. - Open Access
- 13 August 2024
- Published by MDPI AG in Information
- Vol. 15 (8) , 480
AI-Driven QoS-Aware Scheduling for Serverless Video Analytics at the Edge
Today, video analytics are becoming extremely popular due to the increasing need for extracting valuable information from videos available in public sharing services through camera-driven streams in IoT environments. To avoid data communication overheads, a common practice is to have computation close to the data source rather than Cloud offloading. Typically, video analytics are organized as separate tasks, each with different resource requirements (e.g., computational- vs. memory-intensive tasks). The serverless computing paradigm forms a promising approach for mapping such types of applications, enabling fine-grained deployment and management in a per-function, and per-device manner. However, there is a tradeoff between QoS adherence and resource efficiency. Performance variability due to function co-location and prevalent resource heterogeneity make maintaining QoS challenging. At the same time, resource efficiency is essential to avoid waste, such as unnecessary power consumption and CPU reservation. In this paper, we present Darly, a QoS-, interference- and heterogeneity-aware Deep Reinforcement Learning-based Scheduler for serverless video analytics deployments on top of distributed Edge nodes. The proposed framework incorporates a DRL agent that exploits performance counters to identify the levels of interference and the degree of heterogeneity in the underlying Edge infrastructure. It combines this information along with user-defined QoS requirements to improve resource allocations by deciding the placement, migration, or horizontal scaling of serverless functions. We evaluate Darly on a typical Edge cluster with a real-world workflow composed of commonly used serverless video analytics functions and show that our approach achieves efficient scheduling of the deployed functions by satisfying multiple QoS requirements for up to 91.6% (Profile-based) of the total requests under dynamic conditions.
- 13 August 2024
- Published by MDPI AG in Information
- Vol. 15 (8) , 480
Open AccessAI-Driven QoS-Aware Scheduling for Serverless Video Analytics at the Edge
Today, video analytics are becoming extremely popular due to the increasing need for extracting valuable information from videos available in public sharing services through camera-driven streams in IoT environments. To avoid data communication overheads, a common practice is to have computation close to the data source rather than Cloud offloading. Typically, video analytics are organized as separate tasks, each with different resource requirements (e.g., computational- vs. memory-intensive tasks). The serverless computing paradigm forms a promising approach for mapping such types of applications, enabling fine-grained deployment and management in a per-function, and per-device manner. However, there is a tradeoff between QoS adherence and resource efficiency. Performance variability due to function co-location and prevalent resource heterogeneity make maintaining QoS challenging. At the same time, resource efficiency is essential to avoid waste, such as unnecessary power consumption and CPU reservation. In this paper, we present Darly, a QoS-, interference- and heterogeneity-aware Deep Reinforcement Learning-based Scheduler for serverless video analytics deployments on top of distributed Edge nodes. The proposed framework incorporates a DRL agent that exploits performance counters to identify the levels of interference and the degree of heterogeneity in the underlying Edge infrastructure. It combines this information along with user-defined QoS requirements to improve resource allocations by deciding the placement, migration, or horizontal scaling of serverless functions. We evaluate Darly on a typical Edge cluster with a real-world workflow composed of commonly used serverless video analytics functions and show that our approach achieves efficient scheduling of the deployed functions by satisfying multiple QoS requirements for up to 91.6% (Profile-based) of the total requests under dynamic conditions.