Aggelos Ferikoglou

The rapid evolution of Artificial Intelligence (AI) and Machine Learning (ML) has significantly heightened computational demands, particularly for inference-serving workloads. While traditional cloud-based deployments offer scalability, they face challenges such as network congestion, high energy consumption, and privacy concerns. In contrast, edge computing provides low-latency and sustainable alternatives but is constrained by limited computational resources. In this work, we introduce SynergAI , a novel framework designed for performance- and architecture-aware inference serving across heterogeneous edge-to-cloud infrastructures. Built upon a comprehensive performance characterization of modern inference engines, SynergAI integrates a combination of offline and online decision-making policies to deliver intelligent, lightweight, and architecture-aware scheduling. By dynamically allocating workloads across diverse hardware architectures, it effectively minimizes Quality of Service (QoS) violations. We implement SynergAI within a Kubernetes-based ecosystem and evaluate its efficiency. Our results demonstrate that architecture-driven inference serving enables optimized and architecture-aware deployments on emerging hardware platforms, achieving an average reduction of 2.4× in QoS violations compared to a State-of-the-Art (SotA) solution.

High-Level Synthesis (HLS) streamlines FPGA programming by abstracting low-level hardware complexities, facilitating rapid microarchitecture customization through the use of directives. However, identifying optimal directives remains a significant challenge, particularly for software developers without extensive hardware expertise. HLS-driven Design Space Exploration (DSE) addresses this challenge by automating the generation of directive configurations through a variety of techniques. The effectiveness of these methods heavily relies on the quality of the data on which they are built. Unfortunately, existing datasets are often constrained in scope, complexity, and device diversity. To address these limitations, we present GNΩSIS, ¹ the largest open-source HLS dataset, to the best of our knowledge, containing almost 219K design points generated from prominent benchmark suites and public repositories. The dataset covers two FPGAs with varying resource characteristics and three clock frequencies. Additionally, we introduce a versatile framework to automate design point generation. We evaluate the impact of frequency scaling, FPGA architecture, and optimization targets on Quality of Result (QoR) metrics, analyze HLS directive effectiveness across code constructs, and study design transferability across FPGAs and frequencies. These analyses provide practical insights into QoR and HLS behavior, offering guidance for designers with limited optimization experience. We believe GNΩSIS will enhance FPGA accessibility and act as an enabler for innovation in HLS-driven DSE research. The dataset is publicly accessible on Hugging Face, ² and the framework is available on GitHub. ³

This paper proposes a language-level modeling approach for HighLevel Synthesis based on the state-of-the-art Transformer architecture. Our approach estimates the performance and required resources of HLS applications directly from the source code when different synthesis directives, in terms of HLS #pragmas, are applied. Results show that the proposed architecture achieves 96.02% accuracy for predicting the feasibility class of applications and an average of 0.95 and 0.91 R² scores for predicting the actual performance and required resources, respectively.

High-Level Synthesis (HLS) has played a pivotal role in making FPGAs accessible to a broader audience by facilitating high-level device programming and rapid microarchitecture customization through the use of directives. However, manually selecting the right directives can be a formidable challenge for programmers lacking a hardware background. This paper introduces an ultra-fast, knowledge-based HLS design optimization method that automatically extracts and applies the most promising directive configurations to the original source code. This optimization approach is entirely data-driven, offering a generalized HLS tuning solution without reliance on Quality of Result (QoR) models or meta-heuristics. We design, implement, and evaluate our methodology using over 100 applications sourced from well-established benchmark suites and GitHub repositories, all running on a Xilinx ZCU104 FPGA. The results are promising, including an average geometric mean speedup of ×7.2 and ×1.35 compared to designer-optimized designs and resource over-provisioning strategies, respectively. Additionally, it demonstrates a high design feasibility score and maintains an average inference latency of 38ms. Comparative analysis with traditional genetic algorithm-based Design Space Exploration (DSE) methods and State-of-the-Art (SoA) approaches reveals that it produces designs of similar quality but at speeds 2-3 orders of magnitude faster. This suggests that it is a highly promising solution for ultra-fast and automated HLS optimization.

High-Level Synthesis (HLS) has democratized FPGAs by enabling high-level device programmability and rapid microarchitecture customization through the use of directives. Nevertheless, the manual selection of the appropriate directives, i.e. the annotations included in the high-level source code to instruct synthesis process, is a difficult task for programmers without a hardware background. In this paper, we present CollectiveHLS, an ultra-fast knowledge-based HLS design optimization method that automatically extracts the most promising directive configurations and applies them to the original source code. The proposed optimization scheme is a fully data-driven approach for generalized HLS tuning, as it is not based on QoR models or meta-heuristics. We design, implement, and evaluate our method with more than 100 applications of Machsuite, Rodinia, and GitHub on an ZCU104 FPGA. We achieve an average geometric mean speedup of x14.1 and x10.5 compared to the unoptimized, i.e., without HLS directives and optimized designs, a high design feasibility score, and an average inference latency of 38ms.