Nima Maghari

This article presents a new structure of multi-loop continuous-time delta-sigma modulator (CTDSM) with voltage-controlled oscillator-based quantizer (VCO-Q) featuring a robust system with design flexibility and calibration-free. A recent work called correlated dual-loop (CDL) sturdy multi-stage noise-shaping (SMASH) delta-sigma modulator (DSM) removes the explicit quantization error extraction digital-to-analog converter (DAC) needed in conventional multi-loop structures. However, the limited design flexibility and the system’s robustness compromise the application of the CDL. The proposed structure is developed based on the core of the CDL SMASH and addresses its limitations by optimizing the noise transfer function (NTF) and introducing a distributed signal feed-in approach. Furthermore, the signal distribution can also constrain the input swing of the quantizers in our proposed structure. As a result, the VCO-Q, which is limited by nonlinearity issues, can be incorporated well into this design without extra calibration circuits. Fabricated in a 65-nm process, the prototype achieves a 77.2-dB dynamic range (DR) in a 15.625-MHz bandwidth at a 500-MHz sampling rate corresponding to a power consumption of 12.5 mW. The peak Walden figure of merits (FOM) of the proposed design is 97.66 fJ/conv-step with a signal-to-noise-and-distortion ratio (SNDR) of 74 dB.

Physical attacks on secure devices can leak sensitive data and have significant consequences for individuals, companies, and governments. Today, much research is centered around understanding hardware weaknesses and vulnerabilities and, in turn, designing countermeasures to increase system security. One such countermeasure is the implementation of the camouflaging gate called PG-TVD (pass gate-based threshold voltage defined), which ensures protection against reverse engineering and sidechannel attacks. However, proper investigation is needed to determine if the countermeasure opens the door to other powerful attacks, such as laser fault injection (LFI) attacks. Identifying the vulnerability against this attack requires a proper assessment. As the first attempt to understand laser sensitivity in PG-TVD, we develop a workflow for assessing a circuit layout's sensitivity to LFI. We use this workflow to analyze the PG-TVD, giving the laser-sensitive areas. A deeper understanding of how to protect devices can be gained from this assessment to keep sensitive data secure. From the information obtained by our workflow, we also propose, design, and simulate a mitigation scheme that mitigates the laser sensitivity in PG-TVD logic cells by approximately 83%.

As integrated circuit (IC) designs become more and more complex, the globalization of the IC supply chain has become inevitable. Because multiple entities are required to design, fabricate, test, and distribute an IC, the need for reliable security and assurance methods to maintain trust throughout the entire supply chain has never been more critical. This tutorial introduces a variety of mixed-signal approaches to combat electronic counterfeiting. An LDO-based odometer capable of accurately classifying ICs as new or aged is presented as a promising method for detecting counterfeit and recycled ICs. Additionally, this tutorial discusses the use of physical unclonable functions (PUFs) as primitives for generating cryptographic keys for digital signatures, encryption, or authentication. The design process of all PUFs is introduced and the key characteristics and evaluation metrics of state-of-the-art PUFs are defined. Finally, to promote digital IP protection, several methods for camouflaged digital gates are presented and analyzed. The threshold voltage defined (TVD) logic families discussed are capable of implementing any N-to-1 logic function and are highly resilient to reverse engineering attacks.

This article presents a new multi-loop delta-sigma modulator (DSM) structure that combines the advantages of both the traditional multi-stage noise shaping (MASH) and sturdy MASH (SMASH) architectures. It removes the need for an explicit quantization error extraction digital-to-analog converter (DAC) typically required in multi-loop structures, which allows to eliminate the delay mismatch problem related to the intrinsic propagation delay of the first loop quantizer. The proposed architecture essentially uses the SMASH architecture as its core and has similar characteristics. However, it further simplifies the structure allowing to remove all the feedback DACs in the cascaded loop. The prototype DSM fabricated in a 65-nm process achieves signal-to-noise-and-distortion ratio (SNDR) and dynamic range (DR) of 73.4 and 78.3 dB, respectively, in an 18.75-MHz bandwidth. With 1.1/1.5-V (1.5 V for DAC) supply voltage, the prototype DSM consumes 17.85 mW at 600-MHz operating speed corresponding to a Walden and Schreier figure of merits (FOMs) of 124.1 fJ/conv-step and 168.6 dB (using DR result), respectively.

This paper presents a novel physically unclonable function (PUF) for security authentication. Instead of using the variation of transistors or PDK provided passive components as entropy source, the parasitic resistance created between metal and via layers is used as the static entropy source. A symmetric bridge configuration consisted with the parasitic resistance creates the necessary voltage difference for comparison. An accurate backend incremental analog-to-digital converter (IADC) is implemented to convert the voltage difference into a digitized value. The operation of the IADC allows to achieve a good native instability. Two different types of layout structures are implemented to create the necessary parasitic resistance and compared. Fabricated in a 65nm process, the prototype PUF achieves a native instability and bit error rate of less than 1.45% and 0.12% with 5000 repeated evaluations. The proposed design shows 0.58%/0.1V and 0.53%/10°C bit error across the voltage and temperature range of 0.9 to 1.4V and 0°C to 85°C, respectively without any stabilization techniques. The distance ratio between intra-die and inter-die Hamming Distance is above 305x.

This brief presents a more detailed model for the slewing behavior of self-biased ring amplifiers and outlines the factors which affect the large signal operation. A set of analytical expressions derived for the self-biased ring amplifier are presented which are valid for a larger portion of a design space than prior expressions. The equations presented are well matched with simulation results and the accuracy of the derived equations is reported. Finally, the paper examines the proposed equations and simulation results to provide insight about design parameter dependence.

This paper presents an ASIC implementation of a weak physically unclonable function with a bimodal output distribution. The PUF, termed negative impedance based PUF, is formed using a Wheatstone-bridge which employs a combination of positive and negative feedbacks to greatly amplify normally small mismatches due to process variation. The mismatch of the cell skews the overall output impedance to be negative or positive depending on the polarity of the mismatch between feedback paths. The PUF is fabricated in 65nm TSMC LP process. The PUF performance was measured for supply voltages between 0.8 and 1.3 V, and temperatures ranging from 0 C to 80 C. Measurement results show a 1.06% native instability without the use of any digital calibration techniques.

Reverse engineering reveals the physical structure as well as the functionality of an intellectual property (IP) and integrated circuit (IC). This opens the door for IP/IC piracy, counterfeiting, and malicious attacks such as Trojan insertions. Camouflaged logic gates that have the same schematic architecture with identical layout is used to operate for different types of Boolean functions to prevent the de-layering of the chip. An enhanced threshold voltage (E-TVD) defined logic family is proposed in this brief that prevents the internal functionality from being revealed. Compared to previous TVD logic family, the total number of transistors and the cascaded transistors from supply to ground is reduced to enhance the overall performance. A 65nm process is used to compare the conventional TVD logic family and the proposed E-TVD logic family. Post layout simulation results show that the proposed E-TVD logic family for a 3-input logic gate is 34% area efficient, 45% faster, and consumes 40% less power compared to conventional TVD design.

The effect of finite bandwidth of quantizers in continuous-time (CT) delta-sigma modulators (DSMs) is studied. It is shown that the finite quantizer-bandwidth in CTDSMs degrades the performance much more severely than it does in their discrete-time counterparts. It is demonstrated that CTDSMs with excess loop delay (ELD) compensation schemes require an even higher quantizer-bandwidth compared to ELD-free CTDSMs. Furthermore, it is shown that the required quantizer-bandwidth increases as the order and the out-of-band gain increases. Detailed mathematical analyses and simulation results are provided to show the effect of the finite quantizer-bandwidth.

This paper presents a fully synthesized 0.4-V analog biquad filter in a 0.13-μm CMOS technology using digital standard cells. In contrast to a custom-designed inverter-based amplifier in the conventional design, a new NAND-/NOR-gate-based microoperational amplifier (uOP) operating in weak inversion is proposed in this paper. Furthermore, by employing feedforward compensation for loop stability, a new fully synthesized, reprogrammable, multistage operational amplifier (OPAMP) array based on the uOP is introduced which provides variable gain and bandwidth depending on the desired performance. As a proof of concept, a second-order switched-R-MOSFET-C analog filter is implemented. All the active blocks in the analog filter, such as the OPAMPs and matched-RC duty-cycle generator, are implemented using digital gates. The filter is realized using Verilog code and synthesized using automated place and route. The prototype IC achieves 77.17-dB-peak spurious free dynamic range and a tunable bandwidth of 1.7-2.5 MHz while consuming only 0.8 mW of power from a 0.4-V analog supply and a 1-V supply for the switches.