Yizhe Hu

This article presents a Nyquist-rate Analog-to-digital converter (ADC) operating from 0.5 to 2.5 GS/s based on an open-loop resettable ring VCO (R-RVCO). By inherently embedding the $1 {\,}-{\,}z^{-1}$ transfer function, the R-RVCO eliminates the need for an explicit differentiator, suppresses VCO phase-noise (PN) integration, and avoids quantization-noise (QN) shaping within the Nyquist band, yielding a ~3-dB improvement in signal-to-QN ratio (SQNR). To accommodate wide-range input sampling voltages, an adaptive reset technique dynamically adjusts the VCO reset level to maintain the oscillation within its optimal range. A dynamic switched buffer is employed in a coarse quantizer (CQ) and a fine quantizer (FQ) to efficiently capture phase information, reducing hardware complexity and improving energy efficiency. In addition, a predetermined transition sequence enables phase folding (PF) in the FQ, effectively halving the required phase information and associated hardware. Furthermore, a unified theoretical framework is developed to model VCO-based ADC architectures and explain the proposed design’s suitability for multi-gigahertz sampling. Fabricated in 22-nm CMOS, the prototype occupies only 0.0022 mm² and supports sampling rates 500 MS/s–2.5 GS/s. At 2 GS/s, it achieves 39.1-dB signal-to-noise-and-distortion ratio (SNDR), 152.4-dB FoM_S, and 31.3-fJ/conv-step FoM_W. To the authors’ knowledge, this work demonstrates the first standalone VCO-based ADC achieving Nyquist rate operation beyond 2GS/s without time interleaving.

A compact, high-speed 2-bit/cycle prechargeadvancing SAR ADC is proposed. By leveraging an advanced clock timing scheme, the precharge operation of the reference DACs no longer takes extra time but is completed within the sampling period. In addition, a three-stage comparator employing fast discharge technique further enhances conversion speed. The proposed redundancy setting ensures robust ADC performance by correcting errors during operation. Fabricated in a 22nm CMOS process, the 7-bit prototype ADC operates at a 1.41 GS/s sampling rate under a 1V supply, achieving an SNDR of 39.6 dB at Nyquist frequency and a FoM of 23.5 fJ/conversion step, with a total power consumption of 2.59mW. The proposed architecture achieves the highest conversion speed among state-of-the-art single-channel 6–8-bit SAR ADCs.

This article introduces a charge-steering sampling (CSS) technique for time-error detection (TD), an equivalent of phase detection (PD), in phase-locked loops (PLLs). The CSS mechanism presets the input capacitors of a successive approximation register (SAR) analog-to-digital converter (ADC) to $V_{\text {DD}}$ and subsequently discharges them during a reference-triggered pulse through a pseudo-differential MOS pair directly driven by the oscillator. The resulting differential-mode (DM) charge residue, proportional to the time error, is digitized by the ADC to support all-digital PLL (ADPLL) operation. The proposed technique simultaneously achieves high-TD gain for low jitter, the excellent oscillator isolation for reduced reference spur, and multi-bit digital TD output for fast locking, fully leveraging the capabilities of advanced CMOS technology. A digital loop filter (DLF) featuring a dead zone (DZ) in the integral path is introduced to mitigate potential conflicts with the proportional path. To accommodate the short-oscillator period $T_{\text {osc}}$ at millimeter-wave (mm-wave) frequencies, we propose extending the CSS pulsewidth to $1.5\,T_{\text {osc}}$ . In addition, a damped-sine waveform model for the CSS current is developed, providing deeper insights into the high-TD gain characteristics. The comprehensive noise analysis of the CSS is conducted using a multirate timestamp model, identifying contributions to the output phase noise (PN). Fabricated in 22-nm CMOS, the 18.8–23.3-GHz CSS-ADPLL prototype achieves 63-fs rms jitter, −52.4-dBc reference spur, and a figure of merit (FoM) of −254 dB, while consuming 9.95-mW total power, with only 1.3 mW allocated to the loop. For an initial frequency error of 200 MHz, the system achieves a locking time of $0.61~{\mu }$ s, benefiting from the combined effects of a counter-based frequency-locked loop (FLL) ( $0.27~{\mu }$ s) and the multi-bit digital output of the CSS-ADPLL ( $0.34~{\mu }$ s).

We propose a charge-domain fractional-N all-digital phase-locked loop (ADPLL) that employs charge-steering sampling (CSS) of a sinusoidal reference waveform. The well-known issue of $\Delta\!\Sigma$ quantization error in fractional-N operation is compensated by a capacitive digital-to-analog converter (CDAC), which serves the conventional role of a digital-to-time converter (DTC). This CDAC is further merged with the inherent CDAC of a successive approximation register (SAR) analog-to-digital converter (ADC), which is exclusively used for digitizing the time-error mainly induced by the phase noise (PN). Initially, the combined CDACs are preset to V_DD, and then discharged during a short digitally controlled oscillator (DCO)-divider-triggered pulse via a pseudo-differential MOS pair directly driven by the input reference sinusoidal waveform. Owing to the gentle slope of the reference waveform, the charge-domain fractional-N operation achieves a wide and linear time-error detection (TD) range. Furthermore, by reinterpreting the SAR ADC output using multi-bit midrise encoding, the effective time-to-digital conversion (TDC) gain is boosted by bang–bang (BB) effects while maintaining fast and robust locking. To accurately model the CSS current, we introduce a damped-sine waveform model incorporating harmonics, providing comprehensive insight into the CSS-TD gain, even with short-channel devices. Fabricated in 22 nm CMOS, the prototype achieves an rms jitter of 96 fs at 24 GHz with a reference spur of -60 dBc in integer-N mode, while 167.8 fs at approximately 24.5 GHz with a worst in-band spur of -47.8 dBc in fractional-N mode. The occupied area is only 0.08 mm².

A fractional-N frequency synthesizer with low total jitter e.g., <50 fsrms, accounting for both phase noise (PN) and spurs is essential for enabling the emerging 5G/6G and other high-speed wireless communication standards (e.g., WiFi-6/7). While fractional-N phase-locked loops (PLLs) and injection-locking techniques with delta-sigma (ΔΣ) quantization cancellation using a digital-to-time converter (DTC) (and, more recently, DACs) have demonstrated low-jitter performance and are well-understood in terms of PN, their spur mechanisms still lack a comprehensive quantitative analysis. In this paper, we present a unified theoretical framework for spur analysis, based on the time-domain characteristics of spurs, addressing both instantaneous phase modulation and frequency modulation mechanisms. This approach serves as a thorough guide for choosing a low-jitter fractional-N architecture, considering the integral nonlinearity (INL) shaping of DTCs (or DACs) under the control of either a 1st-or 2nd-order ΔΣ modulator (DSM). The framework also extends to reference spurs in both charge-pump PLLs (CP-PLLs) and injection-locked synthesizers. The analytical results of spurs are numerically verified through time-domain behavioral simulations and further validated by experimental results from the literature, thereby demonstrating their effectiveness.

In this article, we present a low phase noise (PN) mm-wave quadrature digitally controlled oscillator (DCO) exploiting transformers for class-F operation and harmonic extraction. A third transformer coil is added for the inter-core coupling with the source terminals of the switching transistors. We identify that the inter-core coupling in quadrature oscillators causes an asymmetric flicker noise current, thus degrading flicker PN. As a remedy, we propose a deliberate drain-to-gate phase shift of the switching transistors by means of capacitive loading to fix this asymmetry. The ±90° I/Q mode ambiguity is also resolved by introducing another phase shift in the source-coupling; it is explained by a simplified analysis with phasor diagrams. Fabricated in the TSMC 28-nm LP CMOS, the prototype achieves PN of −112 dBc/Hz and figure-of-merit (FoM) of −185 dB at 1-MHz offset of 25.7 GHz. The measured flicker PN corner is 140–250 kHz and image rejection ratio (IRR) >47 dB over the whole 18% tuning range (TR). To the best of the authors’ knowledge, it is the best reported PN and IRR for a mm-wave quadrature oscillator.

In this tutorial brief, we introduce a unified wideband phase-noise theory framework of frequency synthesis based on a multirate timestamp modeling with “two $z$ -variables”. We apply it to model and analyze two types of ultra-low jitter (i.e., sub-50fs) phase-locking techniques: 1) high-bandwidth PLLs with high phase-detector gain (with emphasis on all-digital PLLs), and 2) injection locking (IL) or recently proposed charge-sharing locking (CSL), serving as a unified guide on achieving the sub-50 fs jitter. All analytical results are numerically verified through time-domain behavioral simulations, demonstrating that the theoretically maximum bandwidths are around 30% and 44% of the reference frequency in PLLs and IL, respectively.

This article presents a wide-band suppression technique of flicker phase noise (PN) by means of a gate–drain phase shift in a transformer-based complementary oscillator. We identify that after naturally canceling its second-harmonic voltage by the complementary operation itself, third-harmonic current entering the capacitive path is now the main cause of asymmetry in the rising and falling edges, leading to the $1/f$ noise upconversion. A complete $1/f^{3}$ PN analysis for the transformer-based complementary oscillator is discussed. By tuning gate–drain capacitance ratio, a specific phase-shift range is introduced at the gate and drain nodes of the cross-coupled pair to mitigate the detrimental effects of ill-behaved third-harmonic voltage, thus lowering the flicker PN. To further reduce the area and improve the PN in the thermal region, we introduce a new triple-8-shaped transformer. Fabricated in 22-nm FDSOI, the prototype occupies a compact area of 0.01mm ² and achieves $1/f^{3}$ PN corner of 70kHz, PN of −110dBc/Hz at 1MHz offset, figure-of-merit (FoM) of −182dB at 9GHz, and 39% tuning range (TR). It results in the best FoM with normalized TR and area (FoM _TA ) of −214dB at 1MHz offset.

This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant LC -tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate ${z}$ -domain model, supporting any frequency division ratio ${N}$ and CSL (or IL) strength $\beta $ . The new theory sheds light not only on all IL-like PN phenomena (chiefly, its “loop” bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the “loop” cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75—26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.