Teerachot Siriburanon

We introduce a new class-F_3,5 oscillator topology that enables quadrature operation by duplicating a conventional class-F3 oscillator core and electro-magnetically coupling the two cores through a pair of additional coils feeding source terminals of the gm transistors. The coupling network enhances the 5^th-harmonic component, enabling efficient extraction and quadrature operation across the 58.9—73.7-GHz mm-wave frequency range (22.6%). Fabricated in 22nm FD-SOI, the class-F_3,5 oscillator achieves an average phase noise of –124.4 dBc/Hz at a 10MHz offset, resulting in 188/195 dB FoM/FoM_T.

This article presents a single-core, low-phase-noise (PN) digitally controlled oscillator (DCO) employing a pseudo-series resonance (pseudo-SR) technique with a transformer-based resonator. The proposed pseudo-SR resonator offers two key advantages: 1) a low impedance with a 180° phase shift at the impedance pole, emulating series resonance (SR) to enable single-stage oscillation and reduce the power overhead associated with conventional SR oscillators; and 2) flicker PN suppression by aligning the resonant frequencies of the series and parallel tanks, thereby balancing flicker noise exposure over the oscillation cycle. The tank characteristics are analyzed using closed-form derivations based on a transformer-equivalent model, while both thermal and flicker PN are evaluated through the impulse sensitivity function (ISF) framework. To eliminate the need for differential inputs required by conventional SR oscillators, a self-biased inverter is employed in place of an NMOS-only inverter. Fabricated in 28-nm CMOS, the prototype achieves PN of–128.7 and–124.1 dBc/Hz at a 1-MHz offset, with power consumption ( $P_{\text {DC}}$ ) of 36.3 and 33.5 mW at 8.1 GHz ( $f_{\min }$ ) and 9.9 GHz ( $f_{\max }$ ), respectively. The flicker PN ( $1/f^{3}$ ) corner lies between 230 and 380 kHz, and the oscillator core occupies an area of 0.16 mm².

In this article, we present a differentially injection-locked clock multiplier (ILCM) featuring an ultra-wide frequency tuning range (TR) and low jitter, achieved through a compact folded-inductor-based magnetic-flux cancellation technique. A co-designed series-LC dual-mode quadrature ring oscillator (QRO) and edge-combining frequency doubler operating in the mm-wave band jointly extend the TR while suppressing phase noise (PN). Furthermore, a differential time-aligning technique enables an exceptionally wide loop bandwidth ( $f_{\text {BW}}$ ). Fabricated in 28-nm HPC+ CMOS, the prototype QRO exhibits a 59.46% TR (12.25–22.6 GHz), while the doubler output spans 24.5–45.23 GHz. Despite its compact core area of 0.037 mm², the ILCM achieves an rms jitter of 32.83 fs at 39.5 GHz.

Rotary traveling-wave oscillators (RTWOs) are attractive for mm-wave applications due to their ability to efficiently generate multiple phases with compact area and low power consumption. However, their widespread adoption has been hindered by suboptimal phase-noise (PN) performance and the absence of a clear design methodology. In this brief, we analyze the widely studied five-asymmetry RTWO (“5A-RTWO”), identifying key limitations in its PN performance. To address these, we designed a simplified one-asymmetry RTWO (“1A-RTWO”) architecture that achieves a higher quality (Q) factor and improved thermal noise characteristics. Additionally, we investigate the flicker PN upconversion mechanism common to RTWOs. The chosen 1A-RTWO is implemented in 28-nm CMOS and generates 32 evenly spaced phases while operating over 35.2–38.8 GHz. It occupies only 0.03 mm², consumes 16.5 mW, and achieves PN of –102.4 and –127.7 dBc/Hz at 1 and 10 MHz offsets, respectively. The design attains a FoM of 186.5 dBc/Hz at 10 MHz, among the best reported for RTWOs.

This paper analyzes nonlinear effects in digital-totime converters (DTC) operating within the sinusoidal voltage regime of a crystal oscillator (XO), prior to its final conversion into a programmable delayed clock. A detailed theoretical framework models the intrinsic nonlinearities, and a harmonic-based (HB) digital predistortion (DPD) technique is propose to mitigate them. The study explores three key aspects: 1) the intrinsic INL characteristics of the DTC, 2) the interaction between DTC nonlinearity and periodic modulation within the ADPLL feedback path, and 3) practical implementation strategies for HBDPD. Furthermore, a new fractional spur estimation is proposed and validated through behavioral modeling and system-level simulations. Results demonstrate that HB-DPD effectively compensates for the DTC nonlinearities, with performance improving as higher-order harmonics are incorporated. Simulations confirm that applying up to fourth-order harmonic compensation limits the peak-to-peak INL within ±1 LSB (266 fs) and suppresses inband fractional spurs below -70 dBc, closely matching theoretical predictions. These findings confirm the effectiveness of HBDPD in enhancing the linearity and spectral purity of highperformance fractional-N PLLs.

We propose a new ping-pong (PP) charge-sharing locking (CSL) phase-locked loop (PLL) architecture that enhances the strength of charge-injection into the oscillator’s LC-tank using complementary charge-sharing capacitors during both positive and negative halves of the reference clock, effectively achieving an implicit 2× reference frequency multiplication. The design includes a simultaneous frequency-tracking loop (FTL) and duty-cycle calibration (DCC) loop for robust PVT tracking, employing an ultralow-power bang-bang phase-detector (BB-PD). A class-F₃ oscillator along with its third harmonic extractor generate the ~27 GHz output. Implemented in 28 nm CMOS, the PP-CSL PLL demonstrates a threefold increase in injection strength compared to the conventional CSL PLLs, while resolving the load-modulation issue and improving the reference spur by ~15 dB. It achieves an ultralow rms jitter of 42 fs with a power consumption of only 14 mW, resulting in an outstanding jitter-normalized figure of merit (FoM_jitter-N) of -276.6 dB.

To address the relentless increase in data rates in wireless communication systems employing advanced modulation schemes, such as 5G frequency range (FR) 2 [see Figure 1(a)], generating mm-wave signals with minimal integrated phase noise (PN) or RMS jitter is of paramount concern [1]. Figure 1(b) specifies the required jitter to achieve the targeted EVM performance. For instance, for an EVM of less than 3.5%, as needed by a 256-QAM 28-GHz carrier, the RMS jitter contributed by the LO must be below 200 fs. As the carrier frequency or the symbol constellation density increases, the required RMS jitter becomes even more stringent. For example, 1024 QAM at 39 GHz demands an RMS jitter of <50 fs [2], [3], [4].

In this article, we propose a digital-to-time conversion technique operating entirely in the sinusoidal waveform voltage domain of a crystal oscillator (XO) before the signal’s final slicing into the time domain of a programmably delayed clock. Precise timing delay is obtained simply by adjusting the dc offset of the sine signal. A low-complexity sinusoidal-like predistortion linearizes its transfer function. The technique merges the functionality of a digital-to-time converter (DTC) with an XO generation, thus drastically reducing the power consumption of the targeted subsystem while offering a wide range with fine resolution, low noise, and high linearity. Without the requirement for a power-hungry reference buffer/slicer, the proposed DTC benefits from the raw XO waveform, resulting in a large delay coverage and fine resolution. Fabricated in 22-nm fully depleted silicon-on-insulator (FD-SOI) CMOS, the prototype of XO+DTC consumes only 0.52 mW while achieving a 546-ps range with a fine resolution of 266 fs. Its rms jitter (integrated from 1 kHz to 10 MHz) is only 86.6 fs at the output frequency of 100 MHz. Using predistortion of only the fundamental harmonic of a prestored sinusoidal lookup table (LUT), the measured integral nonlinearity (INL) is reduced to $+$ 2/ $-$ 1.9 ps. Together with a higher-harmonic content, such as the second to fourth harmonics, the peak-to-peak INL and DNL is brought down to within $\pm$ 1 LSB (i.e., 266 fs). Based on system modeling of a DTC-assisted all-digital phase-locked loop (ADPLL), the simulated in-band fractional spur (IBFS) can be as low as $-$ 66 dBc.