Naimul Hassan

Toggle spin-orbit torque (SOT)-driven magnetoresistive random access memory (MRAM) with perpendicular anisotropy has a simple material stack and is more robust than directional SOT-MRAM. However, a read-before-write operation is required to use the toggle SOT-MRAM for directional switching, which threatens to increase the write delay. To resolve these issues, we propose a high-speed memory architecture for toggle SOT-MRAM that includes a minimum-sized bit cell and a custom read-write driver. The proposed driver induces an analog self-terminating SOT current that functions via an analog feedback mechanism that can read and write the toggle SOT-MRAM bit cell within a single clock cycle. As the read and write operations are completed within 570 ps, this memory architecture provides the first viable solution for nonvolatile L3 cache.

Securing integrated circuits against counterfeiting through logic locking presents the fundamental challenge of protecting a locking key from physical, Boolean satisfiability (SAT)-based, and structural threats. Prior research has mainly focused on enhancing logic locking to thwart SAT-based and structural attacks but overlooked the necessity of robust physical security. Our work introduces a novel approach: a logic locking scheme utilizing the nonvolatile properties of nanomagnet logic (NML) to provide comprehensive protection. Polymorphic NML minority gates along with conventional locking techniques fortify the locking key against SAT-based and structural threats, while a protective shield, inducing strain in the nanomagnets, offers physical security via a self-destruct mechanism. Although the NML system improves physical security and preserves security against SAT-based and structural attacks, it suffers from drawbacks related to limited reliability and speed, which result in a notable security overhead cost. Consequently, we propose a hybrid CMOS/NML logic locking approach in which NML islands are integrated into a predominantly CMOS-based system. This hybrid solution continues to deliver security against physical, SAT-based, and the known structural attacks while minimizing the associated overhead. We evaluate the security of such hybrid systems against conventional and physically enhanced SAT attacks. The hybrid logic systems are found to retain the security against conventional SAT-based attacks. We further find that these hybrid logic systems are also robust to physically enhanced SAT attacks in which the attacker has access to all internal electrical signals. These hybrid logic systems are thus shown to provide security against all known physical attacks as well as SAT-based attacks, with minimal efficiency tradeoffs resulting from the use of emerging technologies.

The exceptional capabilities of the human brain provide inspiration for artificially intelligent hardware that mimics both the function and the structure of neurobiology. In particular, the recent development of nanodevices with biomimetic characteristics promises to enable the development of neuromorphic architectures with exceptional computational efficiency. In this work, we propose biomimetic neurons comprised of domain wall-magnetic tunnel junctions that can be integrated into the first trainable CMOS-free recurrent neural network with biomimetic components. This paper demonstrates the computational effectiveness of this system for benchmark tasks and its superior computational efficiency relative to alternative approaches for recurrent neural networks.

CMOS devices display volatile characteristics and are not well suited for analog applications such as neuromorphic computing. Spintronic devices, on the other hand, exhibit both non-volatile and analog features, which are well suited to neuromorphic computing. Consequently, these novel devices are at the forefront of beyond-CMOS artificial intelligence applications. However, a large quantity of these artificial neuromorphic devices still require the use of CMOS to implement various neuromorphic functionalities, which decreases the efficiency of the system. To resolve this, we have previously proposed a number of artificial neurons and synapses that do not require CMOS for operation. Although these devices are a significant improvement over previous renditions, their ability to enable neural network learning and recognition is limited by their intrinsic activation functions. This work proposes modifications to these spintronic neurons that enable configuration of the activation functions through control of the shape of a magnetic domain wall track. Linear and sigmoidal activation functions are demonstrated in this work, which can be extended through a similar approach to enable a wide variety of activation functions.

Nanomagnet logic (NML) uses dipolar magnetic coupling between nanomagnets to efficiently perform nonvolatile logical operations. As the basis logic element, the three-input minority gate is the simplest threshold logic function. Recent work has explored the potential for increased logical expressivity with a nanomagnet threshold logic family that reduces area, delay, and energy costs. However, as such previous work was limited to a single layer of nanomagnets, only negative input weights could be provided, thus limiting circuit expressivity and efficiency. This article therefore, proposes multilayer nanomagnet threshold logic systems that provide both positive and negative weights by leveraging multilayer structures that produce both ferromagnetic and antiferromagnetic dipolar coupling. The availability of both positive and negative weights drastically increases logical expressivity, and the feasibility of the proposed multilayer nanomagnet threshold logic system is demonstrated through micromagnetic simulations. A single seven-input gate is shown to perform more than 86 distinct logic functions, reducing the number of gates and clock cycles required for complex logic circuits by as much as 67%.

Spin-orbit torque (SOT) is a promising switching mechanism for magnetic random-access memory (MRAM) as a result of the potential for improved switching speed and energy-efficiency. It is of particular interest to develop an SOT-MRAM device with perpendicular magnetic anisotropy (PMA) in order to leverage the greater density and thermal stability achievable with PMA as opposed to in-plane magnetic anisotropy. However, the orthogonality between SOT and PMA prevents deterministic directional switching without an additional device component that breaks the symmetry, such as an external magnetic field or complex physical structure; not only do these components complicate fabrication, they also are not robust to variations in fabrication and applied switching current. Following previous work demonstrating toggle SOT switching of ferromagnetic layers, this paper therefore proposes a simple SOT-MRAM structure with PMA in which deterministic toggle switching is achieved without requiring additional device components. Furthermore, this toggle PMA SOT-MRAM is shown to be far more robust than previous approaches for directional PMA SOT-MRAM, with no maximum current pulse duration and greater than 50% tolerance to applied switching current magnitude. This paper describes the physical structure and toggle switching mechanism, provides micromagnetic simulations demonstrating its feasibility, and evaluates the robustness and tolerance to material parameters to guide the fabrication of optimized devices that will jumpstart the third generation of MRAM.

Spintronic devices based on domain wall (DW) motion through ferromagnetic nanowire tracks have received great interest as components of neuromorphic information processing systems. Previous proposals for spintronic artificial neurons required external stimuli to perform the leaking functionality, one of the three fundamental functions of a leaky integrate-and-fire (LIF) neuron. The use of this external magnetic field or electrical current stimulus results in either a decrease in energy efficiency or an increase in fabrication complexity. In this article, we modify the shape of previously demonstrated three-terminal magnetic tunnel junction neurons to perform the leaking operation without any external stimuli. The trapezoidal structure causes a shape-based DW drift, thus intrinsically providing the leaking functionality with no hardware cost. This LIF neuron, therefore, promises to advance the development of spintronic neural network crossbar arrays.

The development of an efficient neuromorphic computing system requires the use of nanodevices that intrinsically emulate the biological behavior of neurons and synapses. While numerous artificial synapses have been shown to store weights in a manner analogous to biological synapses, the challenge of developing an artificial neuron is impeded by the necessity to include leaking, integrating, firing, and lateral inhibition features. In particular, previous proposals for artificial neurons have required the use of external circuits to perform lateral inhibition, thereby decreasing the efficiency of the resulting neuromorphic computing system. This work therefore proposes a leaky integrate-and-fire neuron that intrinsically provides lateral inhibition, without requiring any additional circuitry. The proposed neuron is based on the previously proposed domain-wall magnetic tunnel junction devices, which have been proposed as artificial synapses and experimentally demonstrated for non-volatile logic. Single-neuron micromagnetic simulations are provided that demonstrate the ability of this neuron to implement the required leaking, integrating, and firing. These simulations are then extended to pairs of adjacent neurons to demonstrate, for the first time, lateral inhibition between neighboring artificial neurons. Finally, this intrinsic lateral inhibition is applied to a ten-neuron crossbar structure and trained to identify handwritten digits and shown via direct large-scale micromagnetic simulation for 100 digits to correctly identify the proper signal for 94% of the digits.