Christina DiMarino

A coaxial gate/kelvin interconnect is proposed to limit gate loop inductance in vertical package structures. While low-inductance solutions have been demonstrated for planar packages, existing interconnects for vertical package structures result in high inductance per unit length. The coaxial gate/kelvin interconnect proposed here has been shown to reduce per-unit length gate-loop inductances in vertical package structures by 50% or more, enabling more advanced vertical package structures. The proposed on-chip coaxial interconnect also results in significant decoupling between the gate and power loops, enabling faster switching and better control of parallel die. This paper explores several materials and techniques for implementing coaxial interconnects. The resultant electrical characteristics, bond strengths, and viability of these approaches were evaluated. A solution for limiting mechanical stress in the bond between the die and the coaxial interconnects due to mechanical loading on the unbonded end was developed. To demonstrate the viability of the proposed interconnect solution, a package prototype which includes coaxial gate/kelvin interconnects was fabricated and characterized.

Scaled: Substation in a cable for adaptable low-cost electrical distribution: Modern power electronics meets medium voltage cables to create a high-density inline power conversion system for the grid of tomorrow. Global electricity networks face a mounting dual challenge: increased demand and higher risk. Rapid electrification, the accelerated rollout of renewables, and the surging energy appetite of data centers are all straining grid capacity. At the same time, climate change and geopolitical instability raise the stakes for security and resilience. Recent conflicts have highlighted the vulnerability of energy infrastructure during crises, while market volatility has underscored the urgency of building systems that can withstand disruptions. Together, these forces are driving unprecedented stress across transmission and distribution networks.

As next-generation energy technologies gain traction and power demand increases, the existing electrical infrastructure faces significant stress, prompting innovative solutions to enhance the grid’s capacity and lifespan. This work explores the possibility of embedding medium-voltage (MV) power electronics directly inline with the cable, and the resulting thermal challenges. Since the majority of power distribution cables installed in the U.S. are passively cooled, the work focuses primarily on passive cooling, with an emphasis on the limitations of axial heat spreading within the cable. To date, literature on axial spreading of high incident heat loads on cables and cable environments is limited, typically reporting cases with $< $10 W of incident heat load. This work will explore the considerations, limits, and tradeoffs of cable-embedded heat loads significantly larger than the cable losses. Both external and internal effects are modeled analytically in nondimensional terms via a Biot number analysis, allowing fundamental limits and tradeoffs to be derived. The work culminates in the design and experimental validation of a cable-embedded thermal system capable of passively dissipating 300 W of heat from a coaxial SiC mosfet switch module over a length of 20 cm, thus validating the possibility of MV cable-embedded power electronics from a thermal standpoint.

A model-based design process is presented for a generic power converter supporting power-corridor based electrification of Navy ships. The converter topology is a bidirectional resonant CLLC, utilizing a split-core planar transformer and 1.7 kV Gen3 SiC MOSFETs. The components are integrated on connectorless multilayer common substrates for manufacturability, thermal management, and power density. Full-order electrical models are developed in LTSpice for device-level studies, and reduced-order electrical models are developed in PLECS for converter- and system-level studies. The PLECS model is validated by establishing alignment with LTSpice and physical hardware, including a close approximation of switching behaviors. The PLECS model is leveraged for a design space study. Tradeoffs are identified, including soft-switching, frequency, converter power rating, transformer parameters, thermal management, and electromagnetic interference (EMI) mitigation. The chosen design point is validated by a model-based design space study.

A Monte Carlo statistical tolerance analysis is conducted on a parallel-plate, wirebond-less multichip power module (MCPM) to analyze the planarity across modules with post interconnects and identify which parts in the assembly contribute the most variation. Power electronics packaging has migrated from wirebonds to post interconnects that allow for vertical, parallel-plate modules, improving power density, reducing power loop inductances, and enabling double-sided cooled modules. Demonstrations of MCPMs of this structure have been limited in the number of die. This is a substantial gap in literature since as the number of die in parallel increases, the number of post interconnects and bondlines scale, resulting in more variation across component heights and reducing the yield and probability of connecting every interconnect. Different tolerance analyses are discussed and analyzed for the assembly of the MCPM, and a Monte Carlo statistical tolerance analysis is conducted to quantify the maximum height mismatch across the module and identify, which components introduce the most variation. Three MCPMs are fabricated using the statistical tolerance analysis, targeting components to reduce the maximum height mismatch. The 13 kV, six-die module is successfully characterized and is the first functional module of its kind.

This paper presents an overview of thermal management solutions, in support of ship electrification, that are being investigated for power electronic building blocks and their integration into power corridors, both of which are seen as enablers of flexible and reconfigurable power distribution systems in the next generation Navy ships. Air, liquid, two-phase, and indirect cooling approaches are discussed in the context of specific building block configurations built and designed at CPES (Virginia Tech). The paper presents an overview of ongoing efforts towards the design, construction, and testing of cooling technology prototypes.

Electromagnetic interference (EMI) remains a critical roadblock to fully benefitting from the various advantages provided by wide-bandgap devices. Of particular concern is the common-mode (CM) emissions generated during the device operation. This work aims to inform EMI mitigation strategies that can be implemented at the power module design stage and that can result in modules with lower noise emissions in the conducted EMI frequency range. Four 1.2 kV SiC MOSFET power modules are fabricated with different architectures found from literature to better understand their impact on EMI mitigation and to identify trade-offs. Module architectures with integrated CM screens connected to two different DC nodes are experimentally tested and an in-depth analysis on the EMI results is presented. Experimental results show that using a CM screen connected to the DC–link midpoint allows for up to 26 dB of CM current reduction at the baseplate of the module and the input of the converter. Furthermore, this integrated CM screen configuration enables a 0.5% increase in efficiency.

After emerging from the peak of the COVID era, with heavy travel restrictions and less-than-optimal interactions at virtual conferences, we ventured out to our first in-person conferences over the past year. What awaited us was the heartening sight of more women taking up prominent roles in every aspect of the conference. From influential plenary speakers to confident session chairs, passionate presenters, engaged attendees, and dedicated organizers. It served as a powerful reminder that the traditionally male-dominated domain is gradually transforming and becoming more inclusive. While a considerable journey remains ahead, we made unmistakable progress this past year.

This paper presents a printed circuit board (PCB) -embedded 1.2 kV silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) half-bridge package for a 22 kW electric vehicle (EV) on-board charger (OBC). The package meets the application's thermal and electrical requirements while eliminating or reducing factors that drive up manufacturing complexity and footprint in PCBs. Factors such as integration necessity, trace width, and layer count are considered. The package has been prototyped and subjected to electrical and thermal characterization. Static characterization performed on the package prototypes has revealed that the package contributes approximately 0.4 mΩ of parasitic resistance to the power loop. The simulated minimum power-loop and gate-loop inductances of the final package are 2.4 nH and 1.6 nH, respectively. Double pulse tests (DPTs) performed on the final package at 800 V and 25 A revealed that the low loop inductances allow the high-side and low-side switches to achieve 41 V/ns and 37 V/ns turn-off dv/dts , respectively, with drain-to-source voltage (VDS) overshoots of 34 V and 30 V, respectively. The selection of a non-isolated case, along with other design choices, has helped limit the junction-to-case thermal resistance (RTH,JC) of each MOSFET to 0.074 K/W.