Mark Cairnie

A coaxial gate/kelvin interconnect is proposed to limit gate loop inductance in vertical package structures. While low-inductance solutions have been demonstrated for planar packages, existing interconnects for vertical package structures result in high inductance per unit length. The coaxial gate/kelvin interconnect proposed here has been shown to reduce per-unit length gate-loop inductances in vertical package structures by 50% or more, enabling more advanced vertical package structures. The proposed on-chip coaxial interconnect also results in significant decoupling between the gate and power loops, enabling faster switching and better control of parallel die. This paper explores several materials and techniques for implementing coaxial interconnects. The resultant electrical characteristics, bond strengths, and viability of these approaches were evaluated. A solution for limiting mechanical stress in the bond between the die and the coaxial interconnects due to mechanical loading on the unbonded end was developed. To demonstrate the viability of the proposed interconnect solution, a package prototype which includes coaxial gate/kelvin interconnects was fabricated and characterized.

Scaled: Substation in a cable for adaptable low-cost electrical distribution: Modern power electronics meets medium voltage cables to create a high-density inline power conversion system for the grid of tomorrow. Global electricity networks face a mounting dual challenge: increased demand and higher risk. Rapid electrification, the accelerated rollout of renewables, and the surging energy appetite of data centers are all straining grid capacity. At the same time, climate change and geopolitical instability raise the stakes for security and resilience. Recent conflicts have highlighted the vulnerability of energy infrastructure during crises, while market volatility has underscored the urgency of building systems that can withstand disruptions. Together, these forces are driving unprecedented stress across transmission and distribution networks.

As next-generation energy technologies gain traction and power demand increases, the existing electrical infrastructure faces significant stress, prompting innovative solutions to enhance the grid’s capacity and lifespan. This work explores the possibility of embedding medium-voltage (MV) power electronics directly inline with the cable, and the resulting thermal challenges. Since the majority of power distribution cables installed in the U.S. are passively cooled, the work focuses primarily on passive cooling, with an emphasis on the limitations of axial heat spreading within the cable. To date, literature on axial spreading of high incident heat loads on cables and cable environments is limited, typically reporting cases with $< $10 W of incident heat load. This work will explore the considerations, limits, and tradeoffs of cable-embedded heat loads significantly larger than the cable losses. Both external and internal effects are modeled analytically in nondimensional terms via a Biot number analysis, allowing fundamental limits and tradeoffs to be derived. The work culminates in the design and experimental validation of a cable-embedded thermal system capable of passively dissipating 300 W of heat from a coaxial SiC mosfet switch module over a length of 20 cm, thus validating the possibility of MV cable-embedded power electronics from a thermal standpoint.

A Monte Carlo statistical tolerance analysis is conducted on a parallel-plate, wirebond-less multichip power module (MCPM) to analyze the planarity across modules with post interconnects and identify which parts in the assembly contribute the most variation. Power electronics packaging has migrated from wirebonds to post interconnects that allow for vertical, parallel-plate modules, improving power density, reducing power loop inductances, and enabling double-sided cooled modules. Demonstrations of MCPMs of this structure have been limited in the number of die. This is a substantial gap in literature since as the number of die in parallel increases, the number of post interconnects and bondlines scale, resulting in more variation across component heights and reducing the yield and probability of connecting every interconnect. Different tolerance analyses are discussed and analyzed for the assembly of the MCPM, and a Monte Carlo statistical tolerance analysis is conducted to quantify the maximum height mismatch across the module and identify, which components introduce the most variation. Three MCPMs are fabricated using the statistical tolerance analysis, targeting components to reduce the maximum height mismatch. The 13 kV, six-die module is successfully characterized and is the first functional module of its kind.

An automated numerical optimization workflow using Bayesian optimization and a novel weighted point-of-interest (POI) cost function is proposed and demonstrated for PCB-integrated electric field grading structures. The traditional manual design techniques for high-density insulation systems involve simulating the electric field performance and manually assessing the performance characteristics, iterating until an acceptable design is achieved. The proposed technique improves on this by allowing for a fully automated workflow, based on a scalable, computationally efficient cost function that is readily implemented in commercial software and finite element method (FEM) packages. The workflow is demonstrated on PCB-integrated field grading structures, which are employed to alleviate field crowding, and improve field uniformity around the terminals of a high-density 10 kV SiC mosfet power module. The integrated field grading, in conjunction with the module housing, enables a power terminal spacing of 6 mm, while ensuring partial discharge (PD) free operation of the module. The proposed workflow accelerates design time by a factor of three when compared with a competing descent-based technique, and by a factor of 100 when compared with manual design techniques, with seven times lower convergence error. In addition, the optimized system performed 38% better than the previous manually designed version, experimentally demonstrating a PD inception voltage of 11.6 kV rms (16.4 kV peak). The proposed workflow is scalable to larger systems, making it applicable to a broad range of high-density, high-voltage insulation design problems.

Energy innovation trends such as sustainable grids, and the electrification of the consumer transportation market are accelerating the adoption of medium-voltage (MV) silicon-carbide (SiC) technology. The fast switching times and higher operating temperatures enabled by MV SiC have forced package designers to employ innovative technologies to improve power densities, lower stray parasitics, and increase cooling capability. These new technologies ultimately require new simulation tools to allow for fast, efficient, and accurate computation of the multi-physics phenomena that govern package performance. To that end, this work proposes a multi-physics optimization workflow that utilizes reduced-order 3D package models and behavior circuit models to efficiently quantify the effects of the package on converter performance. A cost function is proposed which utilizes the information to optimize for converter performance, rather than individual package parameters.