Shravan K. Chaganti

Distributed measurement networks, from semiconductor testing arrays to environmental sensor grids, medical diagnostic systems, and agricultural monitoring stations, face a fundamental challenge: undetected site-to-site variations that silently corrupt data integrity. These variations create systematic biases between supposedly identical measurement units, which undermine scientific reproducibility and yield. The current site-to-site variation detection methods require extensive sampling or make rigid distributional assumptions, making them impractical for many applications. We introduce a novel framework that transforms measurement data into density-based feature vectors using Kernel Density Estimation, followed by anomaly detection with Isolation Forest. To automate the final classification, we then apply a novel probabilistic thresholding method using Gaussian Mixture Models, which removes the need for user-defined anomaly proportions. This approach identifies problematic measurement sites without predefined anomaly proportions or distributional constraints. Unlike traditional methods, our method works efficiently with limited samples and adapts to diverse measurement contexts. We demonstrate its effectiveness using semiconductor multisite testing as a case study, where our approach consistently outperforms state-of-the-art methods in detection accuracy and sample efficiency when validated against industrial testing environments.

This article explains the application of BIST for co-testing of embedded data converters wherein precision source and measurement requirements are relaxed. This is illustrated for test of DAC and ADC with equal resolution, namely 14 bits. —Rubin A. Parekhjii, Texas Instruments, India

Multi-site testing saves test time and tests cost by screening multiple chips at once. However, it comes with its issues. As test engineers increase the number of sites on each tester to further save test time and cost, variations are now being observed in measurements from site to site which do not correspond to actual problems in the devices under test. Thus, a cost-effective way to investigate site to site variations and identify sites with issues needs to be developed to ensure high test quality and to rule out possible problems arising from the test hardware. In this paper, regression fitting on a quantile-quantile curve is used to compare the distribution of each site to a theoretical and expected distribution. This is shown to pronounce site to site variations inherent in test data, hence identifying issue-ridden sites with ease. The quantile-quantile plot compares the integrals of two probability density functions in a single plot, thus capturing the location, scale, and skewness of the test data set. This method provides more information to the test engineer than classical statistical methods that rely on single test statistics for distribution comparison and is at no extra cost.

A novel ultrafast and low-cost pipelined analog-to-digital converter (ADC) testing and calibration method is proposed. The ADC nonlinearities are modeled as segmented parameters with interstage gain errors. During the test phase, a pure sine wave is sent as input and the model parameters are estimated from the output data with the system identification method. Significantly, fewer samples are required when compared to traditional histogram testing. The modeled errors are then removed from the digital output codes during the calibration phase. Extensive simulations have been run to verify the correctness and robustness of the proposed method. With just 4000 samples, a 12-bit ADC can be accurately tested and calibrated to achieve less than 1 least significant bit (LSB) integral nonlinearity (INL). Measurement results show that the ADC effective number of bits (ENOB) is improved from 9.7to 10.84 bits and the spurious-free dynamic range (SFDR) is improved by 20 dB after calibration. The chip is fabricated in 40-nm technology and consumes 10.71 mW at a sampling rate of 125 MS/s.

Production test of parametric specifications is a significant contributor to the overall cost of build for analog and mixed-signal products. Data converters (ADCs and DACs) in particular are critical components of integrated circuits used in control/actuation and sensing applications. If left un-optimized, their production test time often dominates the overall system-on-chip (SoC) test time. In this paper, we specifically focus on static linearity test of DACs and propose architecture-aware test methods that are combined with best-in-class fast linearity test concepts in the literature to minimize test time without compromising test quality. The proposed methods exploit the hypothesis that the number of device errors which contribute to linearity errors can be captured by a significantly fewer number of variables than the number of codes at which linearity needs to be tested. We introduce a new time and memory efficient method called Extrapolated Reconstruction (ER) to calculate DAC INL and DNL, based on the segmented model introduced in uSMILE. We also demonstrate that since the segmented model techniques do not account for interpolation, they are not suitable for interpolated DACs. We thus develop an interpolated segmented model and enhance both uSMILE and ER to obtain two new methods that provide correct estimations for interpolated DACs. A linearity test time reduction of 15×-20× was seen in actual silicon measurement results for multiple 12-bit DACs and >100× was seen in simulation case studies for many 16-bit DACs.

The Digital-to-Analog-Converter (DAC) is one of the fundamental components of Analog and Mixed-signal circuits. Static linearity testing of high resolution high performance DACs traditionally requires a long time and is very expensive. In this paper, a low-cost ultrafast method of testing DACs is presented. The method utilizes a low cost on-board measurement device for capturing the output of the DAC, instead of a precise digital voltmeter. By using a segmented non-parametric model for the DAC's INL curve and thus reducing the number of unknowns, the test time is drastically reduced. Additionally, the linearity requirement on the measurement device is significantly relaxed by removing its non-linearity. The combination of these two methods results in drastic reduction in linearity test cost for DACs.

Timing jitter is a crucial factor for high speed and high performance ADCs. Random clock jitter and the intrinsic aperture jitter of the ADC raise the noise floor and make it difficult to accurately estimate ADC specifications from the output spectrum. The stringent requirement of coherent sampling imposes further constraints on the test equipment. The proposed method significantly relaxes clock jitter and coherent sampling requirements by utilizing a dual channel test setup. The algorithm can efficiently separate and estimate noise, intrinsic ADC aperture jitter and random clock jitter, while allowing for arbitrary non-coherency in sampling. Simulation results of ADCs of different resolutions and sub-picosecond jitter levels validate the functionality and accuracy of the method.

This paper presents a Concurrent Sampling (CS) method for measuring a multitude of analog DC voltages concurrently using local digitization. Boolean results after digitization are routed in an IJTAG compatible fashion. Analog quantities are no longer routed across the die, thus overcoming several limitations of Analog Test Buses. Furthermore, the proposed method enables real-time measurement of analog voltages, thus addressing a growing need for Automotive test and reliability. The proposed method is applied to an analog circuit consisting of widely used analog blocks such as a bandgap reference and an operational amplifier. Transistor level simulation results demonstrate that the proposed method is functional and the drawbacks of the ATB are no longer present.