Degang Chen

The first divider in an integer- or fractional-N frequency synthesizer runs at the full oscillator frequency and so constrains both the speed and the power of the loop. Current-mode logic (CML) reaches high speed but draws a constant bias current independent of activity, whereas a fully static-CMOS (all-digital) divider draws only dynamic and leakage current at the cost of much greater timing sensitivity to process, voltage, and temperature (PVT) variation. This paper presents a wide-range all-digital multi-modulus divider in a 22 nm fully depleted silicon-on-insulator (FDSOI) technology, characterized entirely by post-layout and Monte Carlo simulation, together with the methodology that makes the timing-sensitive digital approach robust. The all-digital chain exhibits three PVT failure modes, setup at the slow-hot corner, hold at the fast-cold corner, and internal duty-cycle collapse at the skewed corners; each is predicted analytically and closed by a three-method scheme built on the FDSOI back gate, a per-stage delay trim, and a systematic integral-nonlinearity trim. The divider covers N=8 to 127 at up to 39.5 GHz at the typical corner, with every process corner held at or above 35 GHz by back-gate compensation, the highest speed among the compared dividers and the only one with explicit PVT compensation. At the 33 GHz target it consumes 5.3 mW at N=127 (6.2 GHz/mW) with an activity-scaling supply current, benchmarked against the measured power of published CML dividers. Per-die body-bias and trim raise the Monte Carlo yield from 78% to 99.3%, at 150 fs additive jitter, in a compact 0.005 mm² core.

This paper presents a precision, wide-dynamic-range leakage current sensor tailored for in-situ monitoring of aging mechanisms such as Time-Dependent Dielectric Breakdown (TDDB) in both active and passive components. The proposed architecture supports high-voltage stress and is fully monolithic, integrating a current-to-voltage front-end, tunable gain amplifier, and a successive approximation register (SAR) analog-to-digital converter (ADC). To validate the concept, a discrete-component prototype was implemented and evaluated across a leakage current range of 1nA to 1 μA. The sensor achieves 12-bit resolution with measured integral nonlinearity (INL) and differential nonlinearity (DNL) within ±1.5 LSB and ±0.3 LSB, respectively. Compared to prior monitors, the design enables linear current digitization and compatibility with high-voltage stress, features essential for accurate and scalable TDDB characterization. Applications include embedded reliability monitoring in power converters, analog building blocks, and large-scale aging test arrays.

This paper presents a novel methodology for the design and calibration of ultra-compact digital-to-analog converters (DACs), integrating architectural redundancy and a digital calibration algorithm. The proposed calibration approach generates pre-distortion codes that correct both positive and negative nonlinearity errors, even in designs with severe mismatch or relaxed layout constraints. This enables the use of aggressively scaled devices while maintaining high linearity and spectral fidelity. The algorithm is architecture-agnostic and compatible with resistor-string, current-steering, and hybrid DAC structures. It operates with minimal memory, low latency, and supports both foreground and background calibration modes. The method is validated through simulation and silicon measurement of three 14-bit DAC architectures fabricated in TSMC 180 nm CMOS. Post-calibration results demonstrate linearity within ±0.5–1.2 LSB, ENOB up to 13.8 bits, and significant improvements in SNR, SFDR, and THD. The compact layouts—occupying as little as 0.0169 mm²—highlight the scalability of the proposed method for applications such as analog AI accelerators and high-density mixed-signal SoCs.

Distributed measurement networks, from semiconductor testing arrays to environmental sensor grids, medical diagnostic systems, and agricultural monitoring stations, face a fundamental challenge: undetected site-to-site variations that silently corrupt data integrity. These variations create systematic biases between supposedly identical measurement units, which undermine scientific reproducibility and yield. The current site-to-site variation detection methods require extensive sampling or make rigid distributional assumptions, making them impractical for many applications. We introduce a novel framework that transforms measurement data into density-based feature vectors using Kernel Density Estimation, followed by anomaly detection with Isolation Forest. To automate the final classification, we then apply a novel probabilistic thresholding method using Gaussian Mixture Models, which removes the need for user-defined anomaly proportions. This approach identifies problematic measurement sites without predefined anomaly proportions or distributional constraints. Unlike traditional methods, our method works efficiently with limited samples and adapts to diverse measurement contexts. We demonstrate its effectiveness using semiconductor multisite testing as a case study, where our approach consistently outperforms state-of-the-art methods in detection accuracy and sample efficiency when validated against industrial testing environments.