Yuriko Maegami

Multi-Tb/s optical interconnects for artificial intelligence data centers necessitate high-speed, energy-efficient, and compact transceivers. However, conventional silicon Mach-Zehnder modulators are fundamentally limited by low modulation efficiency and large physical dimensions that typically extend several millimeters, requiring high-swing drivers and power-intensive digital signal processing to achieve data rates exceeding 100 Gb/s per lane. Here we show a silicon photonic crystal waveguide slow-light modulator that overcomes the bandwidth-efficiency trade-off via a built-in electro-optic equalizer. By monolithically integrating optical delay lines and crossings within segmented slow-light phase shifters, we synthesized an on-chip feedforward response that extends the 3-dB bandwidth. The fabricated modulator with a small device length of 320 µm demonstrated 140-Gb/s on-off keying operation with an energy consumption of 26 fJ/bit using drive voltages compatible with fin field-effect transistor-based complementary metal-oxide-semiconductor technology. Furthermore, four-level pulse amplitude modulation achieved 180 Gb/s without digital signal processing and 200 Gb/s with a low-complexity 11-tap digital equalizer. By reducing reliance on power-dissipating electronics, this strategy provides a potential route toward future dense multi-Tb/s co-packaged optics for energy-constrained switching systems.

As Moore’s law approaches its limit, the search for alternative computing platforms beyond conventional digital electronics is intensifying. Photonic interferometric processors offer a route to ultrahigh-throughput computing by exploiting the spatial, temporal, and wavelength degrees of freedom of light. However, scaling such systems has remained a major challenge due to the lack of robust calibration strategies for large interferometric meshes subject to fabrication disorder and crosstalk. Here, we present a scalable silicon photonic interferometric complex-valued matrix processor. This is achieved by introducing a newly developed disorder-aware calibration framework that directly infers circuit parameters and crosstalk from input–output measurements, eliminating the need for auxiliary monitoring structures. This approach enables high-fidelity operation of large-scale interferometric meshes beyond the regime accessible with conventional calibration methods. We experimentally demonstrate a 16 × 16 processor achieving near-ideal complex-valued matrix operations, including MNIST classification without off-chip electronic neural networks. Importantly, we further demonstrate wavelength-insensitive operation across 86 channels over a 2.2-THz bandwidth without recalibration, enabling simultaneous scaling in both spatial and wavelength domains within a single processor. Our results establish a scalable architecture for interferometric photonic computing and open a path toward ultrahigh-throughput matrix–matrix multiplication using wavelength-division multiplexing.

Increasing datacenter demands require power-efficient optical interconnects. However, a conventional standard transmitter using a silicon rib-waveguide Mach-Zehnder modulator and voltage-mode driver has low efficiency and consumes watt-class high power and occupies a several-square-millimeter footprint, which limits large-scale integration for parallel transmission. This paper presents a transmitter consisting of a compact photonic crystal waveguide (PCW) modulator and a current-mode open-collector driver. The PCW modulator is designed to have high impedance in addition to the slow-light effect. The driver connected to the modulator without termination resistors is optimized based on electronics-photonics co-simulations using a standard electronic circuit simulator with an in-house photonic model library. Co-packaging these dramatically reduces the power consumption to 50 mW and a bit energy to 0.78 pJ/bit at 64-Gbaud, and the footprint to 0.66 mm². This result represents a significant advancement toward the integration of a large number of transmission channels with no temperature control.

We propose a silicon photonics fiber coupler consisting of a metastructure containing a through-hole array and a partially etched grating to obtain high efficiency. Using an evolution optimization algorithm, we optimized 121 structural parameters and achieved a minimum feature size of 150 nm, which greatly simplifies the fabrication using wafer-scale foundry services. We designed two structures, one achieving an 86% coupling efficiency into a single fiber, and the other exhibiting a full flat spectrum in the C band. The high-efficiency structure was fabricated using a 300-mm wafer process, and an efficiency of 78% was experimentally evaluated.

Silicon modulators in optical transceivers feature high-density integration and low manufacturing cost, but they also need to deliver high speed and low power consumption to meet the demands of future data centers and high-performance computing. This paper demonstrates a significantly improved 64 Gbps silicon Mach–Zehnder modulator incorporating photonic crystal slow-light phase shifters. By employing distributed electrodes and engineering their impedance, electro-optic phase matching and electrical impedance matching were obtained simultaneously, and the driving voltage was reduced to 0.87 V, which is compatible with fin-type field effect transistors and eliminates the need for additional electrical amplifiers. The bit energy of as low as 59 fJ/bit is comparable to that of microring modulators, while this modulator does not require temperature control like that used for microring modulators, due to its wide working spectrum of 6 nm. These results indicate the potential for addressing power issues in next-generation data infrastructures.

Integrated photonic neural networks (PNNs) usually adopt traditional convolutional neural network (CNN) or multilayer perceptron (MLP) network models. These models consist of horizontally cascaded deep layer architectures interleaved by nonlinear activation functions. However, there are practical challenges for on-chip realizing such architectures, including the optical loss and the lack of efficient on-chip optical activation nonlinearity. Here, we propose a vertically hierarchical photonic neural network leveraging electro-optical element-wise multiplication to extract an element-wise feature in a polynomial projection space, which enables high-accuracy classification. For this network architecture, the light propagates through only two fully connected linear layers; thus, vertical extension to the deep layer is not limited by optical loss. This electro-photonic network can perform equivalently to or outperform optical CNN and MLP models even without interleaving deep layers by activation functions, benchmarking ∼97.9%, ∼87.7%, and ∼90.3% average blind-testing accuracies, for the whole test sets of MNIST handwritten digits, Fashion-MNIST images, and KMNIST Japanese cursive characters, respectively. It also demonstrates a >99% accuracy for boundary prediction of 12-labeled clusters. This work presents a different PNN architecture, which offers both high performance and better amenability to an integrated photonics platform.

We demonstrate a reversible and non-volatile optical phase shift in a silicon-nitride waveguide by a process of thermal annealing and ultraviolet irradiation, and investigate a correlation between phase shifts and charge state of dangling bonds.

On-chip training remains a challenging issue for photonic devices to implement machine learning algorithms. Most demonstrations only implement inference in photonics for offline-trained neural network models. On the other hand, artificial neural networks are one of the most deployed algorithms, while other machine learning algorithms such as supporting vector machine (SVM) remain unexplored in photonics. Here, inspired by SVM, we propose to implement projection-based classification principle by constructing nonlinear mapping functions in silicon photonic circuits and experimentally demonstrate on-chip bacterial foraging training for this principle to realize single Boolean logics, combinational Boolean logics, and Iris classification with ~96.7 − 98.3 per cent accuracy. This approach can offer comparable performances to artificial neural networks for various benchmarks even with smaller scales and without leveraging traditional activation functions, showing scalability advantage. Natural-intelligence-inspired bacterial foraging offers efficient and robust on-chip training, and this work paves a way for photonic circuits to perform nonlinear classification.

We present applications of a CMOS-compatible SiN waveguide to an ultralow-loss fiber coupling structure and a Si-to-SiN waveguide on a Si photonics platform for C-band infrared light. We also evaluate waveguide properties for visible light.

Silicon Mach-Zehnder modulators (MZMs) utilizing carrier depletion usually adopt traveling-wave (TW) electrodes for their long phase shifters, which have inherent challenges in miniaturization, limiting the integration density of monolithic transceivers. In this work, we experimentally demonstrate non-TW carrier-depletion MZMs that give better compromises between compact footprint, modulation depth, and high speed. They adopt densely meandered phase shifters and thus offer an ultra-compact lumped-element MZM for using carrier depletion. Up to 28.1 Gb/s NRZ eye diagrams and ~26 GHz electro-optic bandwidth were experimentally achieved. The proposed lumped circuit model well explains the experimental data, indicating that impedance mismatching is the dominant factor in determining experimental bandwidth and a LC resonance contributes to the bandwidth improvement. Driving configurations with better impedance matching are proposed to further improve bandwidth. This novel MZM can enhance the integration density of modulators in wavelength-division multiplexing transceivers.