Xinfei Guo

Contrast-Limited Adaptive Histogram Equalization (CLAHE) is widely used in industrial and embedded imaging, yet a fixed Clip Limit often fails to balance detail enhancement and noise suppression across diverse scenes while maintaining stall-free, one-pixel-per-cycle pixel-stream throughput. This article proposes a deployment-driven, perception-guided software–hardware co-design for CLAHE, where perceptual guidance from offline no-reference image quality assessment (NR-IQA) signals is distilled into a low-dimensional policy that only consumes hardware-observable statistics, and the field-programmable gate array (FPGA) architecture embeds closed-loop control without stalling the main pixel path. On the learning side (offline, in software), Clip Limit tuning is formulated as a Markov decision process (MDP) and learned with Soft Actor-Critic (SAC) using a dual-teacher distillation scheme that transfers privileged NR-IQA guidance to a low-dimensional student policy. Posterior trajectory selection (PTS) and Q4.12 quantization-aware distillation further improve robustness under partial observability and fixed-point inference. On the hardware side, we implement an FPGA single-clock-domain streaming pipeline that integrates feature extraction, student inference, and CLAHE mapping while preserving one-pixel-per-cycle throughput, and we reduce critical-path complexity via division elimination and separable fixed-point interpolation. The controller performs one update per frame and commits the new Clip Limit at the frame boundary; therefore, a five-step horizon corresponds to a five-frame gradual adaptation with intra-frame consistency. Experiments show that the proposed controller is competitive with strong fixed-parameter baselines in mean NR-IQA scores, while reducing failure-sensitive upper-tail degradation using hardware-observable inputs only.

Reliability is an increasing concern in modern computing. Integrated circuits (ICs) form the backbone of computing devices across industries, including AI, consumer electronics, healthcare, automotive, industrial, and aerospace. While Moore’s Law has driven ICs toward smaller dimensions, higher performance, and greater energy efficiency, transistor scaling to atomic levels has exacerbated aging-related degradation mechanisms such as Bias Temperature Instability (BTI), Hot Carrier Injection (HCI), Time-Dependent Dielectric Breakdown (TDDB), Electromigration (EM), and stochastic aging-induced variations. Applications like AI training and autonomous driving demand continuous, reliable operation to minimize recovery costs and enhance safety. Additionally, the high cost of chip replacement underscores the need for extended lifespans. These challenges highlight the urgency of designing more reliable ICs as critical computing infrastructure. This survey explores aging in ICs, covering key degradation mechanisms and mitigation strategies. It provides a comprehensive overview of aging’s impact, key monitoring techniques at circuit and system levels, and circuit-level mitigation strategies tailored for digital, analog, and SRAM circuits. The survey also examines emerging software-driven approaches in design automation and aging characterization, which are transforming traditional reliability optimization. Finally, it discusses challenges and future directions to improve aging management and ensure long-term IC reliability across applications.

The chip design process involves numerous steps, beginning with defining product requirements and progressing through architectural planning, system-level design, and the physical layout of individual circuit blocks. As the enablers of large-scale chip development, Electronic Design Automation (EDA) tools play a vital role in helping designers achieve high-quality results. The Shift-Left methodology introduces a pathway toward creating digital twins and fusing multiple design steps, thereby transitioning traditionally sequential, physically-aware processes into virtual design environments. As late-stage fixes are often prohibitively expensive, this shift allows designers to establish stronger correlations earlier and optimize designs more effectively. However, challenges remain, especially in accurately replicating downstream behaviors and determining the right scope and timing for adoption. These challenges, in turn, have revealed new opportunities for EDA vendors, physical designers, and logic designers alike. The rise of AI techniques and the momentum of open-source design flows have also significantly strengthened prediction and modeling capabilities, making data-driven methods increasingly relevant to the EDA community. This, in turn, enhances the “Shift-Left” features embedded in current tools by enabling AI-assisted prediction of downstream design metrics earlier in the flow. As the industry advances toward intelligent EDA tools and techniques, it is timely to reflect on Shift-Left progress made and the challenges that remain. In this article, we present a comprehensive survey of existing and emerging paradigms in Shift-Left research within EDA and the broader design ecosystem. Our goal is to provide a unique perspective on the state of the field and its future directions. Relevant articles mentioned are organized in https://github.com/iCAS-SJTU/Shift-Left-EDA-Papers.

Physical dataflow, which defines the detailed connections among cells and macros, is a critical yet underexplored factor in automatic macro placement. It becomes increasingly important for enabling intelligent design automation to minimize manual intervention and reduce design iterations. Existing macro or mixed-size placers with dataflow awareness primarily focus on intrinsic relationships among macros, overlooking the crucial influence of standard cell clusters on macro placement. To address this, we propose DARE, which extracts hidden connections between macros and standard cells and incorporates a series of algorithms to enrich dataflow awareness, integrating them into placement constraints for improved macro placement. To further optimize placement results, we introduce two fine-tuning steps: (1) congestion optimization by taking macro area into consideration, and (2) flipping decisions to determine the optimal macro orientation based on the extracted dataflow information. By integrating enhanced dataflow awareness into placement constraints and applying these fine-tuning steps, the proposed approach achieves an average 7.9% improvement in half-perimeter wirelength (HPWL) across multiple widely used benchmark designs compared to a state-of-the-art dataflow-aware macro placer. Additionally, it significantly improves congestion, reducing overflow by an average of 82.5%, and achieves improvements of 36.97% in Worst Negative Slack (WNS) and 59.44% in Total Negative Slack (TNS). The approach also maintains efficient runtime throughout the entire placement, incurring less than a 1.5% runtime overhead. These results show that the proposed dataflow-driven methodology, combined with the fine-tuning steps, provides an effective foundation for macro placement within the OpenROAD flow and can be further extended to other design flows in the future to enhance placement quality.

This paper introduces R-Zoo, a comprehensively developed and rigorously validated benchmark dataset of rectilinear floorplans designed for research in electronic design automation (EDA) and physical chip design. Existing public floorplanning benchmarks are predominantly restricted to simplified rectangular blocks, offering limited structural variability and design realism. R–Zoo addresses these limitations by introducing a large-scale, reproducible collection of legally verified rectilinear layouts that capture the complexity of modern system-on-chip (SoC) designs. R-Zoo captures a broad range of rectilinear geometries and layout scales, reflecting differences in aspect ratio, module complexity, and whitespace organization. This ensures that R-Zoo remains representative of practical design conditions rather than idealized academic abstractions. The R-Zoo integrates user-directed customization, computer-vision-assisted reconstruction, and large language model (LLM)-guided batch generation to achieve controllable diversity and scalability. All generated designs undergo rigorous LLM-based legality checking and image–layout consistency validation to ensure industrial compliance and physical correctness. Containing thousands of rectilinear floorplans across seven representative SoC designs, R-Zoo establishes a standardized and extensible platform for evaluating geometry-aware floorplanning algorithms, training learning-based placement models, and serving as an open reference library for the EDA community. By bridging the gap between traditional rectangular benchmarks and modern rectilinear-aware optimization research, R-Zoo provides a new foundation for reproducible and data-driven floorplan design studies.

This paper introduces the Verilog Core Dataset (CORE), a systematically curated corpus of 137 synthesizable Verilog HDL modules spanning 24 distinct categories of digital logic designs Unlike existing RTL benchmark suites that suffer from outdated designs, inconsistent quality, and limited configurability, CORE is purpose-built to address these limitations through a rigorous methodology that combines large language model (LLM)-assisted code generation, human expert refinement, and comprehensive verification pipelines. Each module is accompanied by a respective testbench for functional simulation, and adheres to Verilog-1995 and SystemVerilog-2012 standards, ensuring broad tool compatibility and synthesis readiness. CORE’s parameterized and scalable designs enable structural variation, making it uniquely suited for ML4EDA research, design-space exploration, and Design-Technology Co-Optimization (DTCO) workflows. By offering a reproducible, extensible, and standards-compliant RTL corpus, CORE establishes a new foundation for benchmarking, education, and innovation in digital system design.