Xiaotian Zhao

The chip design process involves numerous steps, beginning with defining product requirements and progressing through architectural planning, system-level design, and the physical layout of individual circuit blocks. As the enablers of large-scale chip development, Electronic Design Automation (EDA) tools play a vital role in helping designers achieve high-quality results. The Shift-Left methodology introduces a pathway toward creating digital twins and fusing multiple design steps, thereby transitioning traditionally sequential, physically-aware processes into virtual design environments. As late-stage fixes are often prohibitively expensive, this shift allows designers to establish stronger correlations earlier and optimize designs more effectively. However, challenges remain, especially in accurately replicating downstream behaviors and determining the right scope and timing for adoption. These challenges, in turn, have revealed new opportunities for EDA vendors, physical designers, and logic designers alike. The rise of AI techniques and the momentum of open-source design flows have also significantly strengthened prediction and modeling capabilities, making data-driven methods increasingly relevant to the EDA community. This, in turn, enhances the “Shift-Left” features embedded in current tools by enabling AI-assisted prediction of downstream design metrics earlier in the flow. As the industry advances toward intelligent EDA tools and techniques, it is timely to reflect on Shift-Left progress made and the challenges that remain. In this article, we present a comprehensive survey of existing and emerging paradigms in Shift-Left research within EDA and the broader design ecosystem. Our goal is to provide a unique perspective on the state of the field and its future directions. Relevant articles mentioned are organized in https://github.com/iCAS-SJTU/Shift-Left-EDA-Papers.

Physical dataflow, which defines the detailed connections among cells and macros, is a critical yet underexplored factor in automatic macro placement. It becomes increasingly important for enabling intelligent design automation to minimize manual intervention and reduce design iterations. Existing macro or mixed-size placers with dataflow awareness primarily focus on intrinsic relationships among macros, overlooking the crucial influence of standard cell clusters on macro placement. To address this, we propose DARE, which extracts hidden connections between macros and standard cells and incorporates a series of algorithms to enrich dataflow awareness, integrating them into placement constraints for improved macro placement. To further optimize placement results, we introduce two fine-tuning steps: (1) congestion optimization by taking macro area into consideration, and (2) flipping decisions to determine the optimal macro orientation based on the extracted dataflow information. By integrating enhanced dataflow awareness into placement constraints and applying these fine-tuning steps, the proposed approach achieves an average 7.9% improvement in half-perimeter wirelength (HPWL) across multiple widely used benchmark designs compared to a state-of-the-art dataflow-aware macro placer. Additionally, it significantly improves congestion, reducing overflow by an average of 82.5%, and achieves improvements of 36.97% in Worst Negative Slack (WNS) and 59.44% in Total Negative Slack (TNS). The approach also maintains efficient runtime throughout the entire placement, incurring less than a 1.5% runtime overhead. These results show that the proposed dataflow-driven methodology, combined with the fine-tuning steps, provides an effective foundation for macro placement within the OpenROAD flow and can be further extended to other design flows in the future to enhance placement quality.

This paper introduces R-Zoo, a comprehensively developed and rigorously validated benchmark dataset of rectilinear floorplans designed for research in electronic design automation (EDA) and physical chip design. Existing public floorplanning benchmarks are predominantly restricted to simplified rectangular blocks, offering limited structural variability and design realism. R–Zoo addresses these limitations by introducing a large-scale, reproducible collection of legally verified rectilinear layouts that capture the complexity of modern system-on-chip (SoC) designs. R-Zoo captures a broad range of rectilinear geometries and layout scales, reflecting differences in aspect ratio, module complexity, and whitespace organization. This ensures that R-Zoo remains representative of practical design conditions rather than idealized academic abstractions. The R-Zoo integrates user-directed customization, computer-vision-assisted reconstruction, and large language model (LLM)-guided batch generation to achieve controllable diversity and scalability. All generated designs undergo rigorous LLM-based legality checking and image–layout consistency validation to ensure industrial compliance and physical correctness. Containing thousands of rectilinear floorplans across seven representative SoC designs, R-Zoo establishes a standardized and extensible platform for evaluating geometry-aware floorplanning algorithms, training learning-based placement models, and serving as an open reference library for the EDA community. By bridging the gap between traditional rectangular benchmarks and modern rectilinear-aware optimization research, R-Zoo provides a new foundation for reproducible and data-driven floorplan design studies.

Layer-wise mixed-precision quantization (MPQ) has become prevailing for edge inference since it strikes a better balance between accuracy and efficiency compared to the uniform quantization scheme. Existing MPQ strategies either lacked hardware awareness or incurred huge computation costs, which gated their deployment at the edge. In this work, we propose a novel MPQ search algorithm that obtains an optimal scheme by "sampling" layer-wise sensitivity with respect to a newly proposed metric that incorporates both accuracy and proxy of hardware cost. To further efficiently deploy post-training MPQ on edge chips, we propose to tightly integrate the quantized inference units as part of the processor pipeline through micro-architecture and Instruction Set Architecture (ISA) co-design. Evaluation results show that the proposed search algorithm achieves 3% ~ 11% higher inference accuracy with similar hardware cost compared to the state-of-the-art MPQ strategies. In addition, the tightly integrated MPQ units achieve speedup of 15.13x ~ 29.65x compared to a baseline RISC-V processor.

In this article, an orthogonal 6-degree-of-freedom (DOF) parallel robot with redundant actuation is studied as an earthquake motion simulator. Taking the practical simulation of earthquake waves into consideration, the general characteristics of natural earthquakes are analysed and complexity and variety of seismic waves, three-dimensional and multi-DOF movement, and strong devastating force are regarded as the three obvious features in this article. Based on the characteristics of this orthogonal 6-DOF parallel robot with redundant actuation and the features of earthquakes, the feasibility of using this parallel robot as an earthquake motion simulator is analysed from three aspects: orthogonal 6-DOF structure, decoupling feature, and redundant actuation module. In order to simulate an earthquake motion using this parallel robot, its inverse kinematics and dynamics models are derived. The control system of this earthquake simulator is developed based on the PXIbus development platform. The computed-torque control algorithm based on the inverse dynamics is used in the controller of this equipment. A typical three-directional earthquake motion, the El Centro earthquake, is simulated on the end-effector of this parallel robot by means of its mathematical models and control system. Three main motion parameters of simulated seismic waves, displacements, velocities, and accelerations, are measured, respectively, by laser tracker and acceleration sensors. The experimental results show this equipment is appropriate to be used as an earthquake simulator.