Hao Gu

Floorplanning is a critical phase in VLSI physical design, focusing on determining block positions while optimizing wirelength under specified area constraints. However, classical analytical-based floorplanners are highly sensitive to the quality of initial solutions, and existing learning-based methods often suffer from high computational inefficiency and complexity. In this paper, we propose a customized diffusion model to directly generate high-quality initial floorplans. By leveraging a classical analytical-based floorplanner on top of this initial floorplan, the final floorplanning results are significantly improved. To enhance feature extraction, a heterogeneous graph neural network (HGNN) is developed to explicitly incorporate block-to-block and pin-to-block relationships from the netlist during the diffusion process. We further propose a classifier-free conditional diffusion method based on adaptive maximum-mean discrepancy (Ada-MMD) to guide the generation process without relying on external classifiers. The Ada-MMD mechanism adaptively captures structural correlations in the latent space, improving conditional consistency and enabling more controllable and accurate initial floorplan generation. Additionally, a novel guidance sampling function is introduced to optimize both wirelength and overlap, effectively reducing the required sampling steps while maintaining competitive initial solutions. Experimental results demonstrate that integrating our proposed diffusion model with an advanced analytical-based floorplanner achieves at least 10.8% reduction in runtime and 3.8% reduction in HPWL compared to the original state-of-the-art floorplanner and other diffusion-based methods.

Field-programmable gate array (FPGA) macro placement holds a crucial role within the FPGA physical design flow since it substantially influences the subsequent stages of cell placement and routing. With the increasing number of macros and the complex cascade shape and region constraints imposed by modern FPGAs, the routability and macro placement have become much more challenging. In this article, we propose an effective and efficient routability-driven macro placement algorithm for modern FPGAs with cascade shape and region constraints. To reserve adequate space for cell placement and guarantee routability, we first develop a routability-driven mixed-size analytical global placement that evenly distributes both macros and cells while considering cascade shape and region constraints. Particularly, the proposed global placement engine integrates a well-trained congestion prediction model, targeting benchmarks with high routing congestion to enhance overall routability. Then, we propose an integer linear programming (ILP)-based cascade shape legalization followed by matching-based macro legalization to remove macro overlaps while satisfying the region constraints. Finally, a routability-driven detailed macro placement is proposed to refine the solution. Compared with the winners of the MLCAD 2023 FPGA macro placement contest and state-of-the-art works, experimental results show that our algorithm achieves the best overall score and routability.

In very large scale integration (VLSI) circuit physical design, precise congestion prediction during placement is crucial for enhancing routability and accelerating design processes. Existing congestion prediction models often encounter challenges in handling multimodal information and lack effective fusion of placement and netlist features, limiting their prediction accuracy. In this paper, we present a novel congestion prediction model that leverages dual multimodal fusions with convolution and transformer layers to effectively capture the multiscale placement information and enhance congestion prediction accuracy. We first adopt convolutional neural networks (CNN) to extract grid-based placement features and heterogeneous graph convolutional networks (HGCN) to extract netlist information. To help the model understand the correlation between different modalities, we then propose an early feature fusion (EFF) to integrate netlist knowledge into multiscale placement features at multimodal interaction subspace. Besides, a deep feature fusion (DFF) method is proposed to further fuse multimodal features, which has multiple vision transformer layers based on adaptive attention enhancement technology. These layers include self-attention to boost intra-modal features and cross-attention to perform cross-modal feature fusion on netlist and grid-based placement features. Finally, the output features of DFF are sent into the cascaded decoder to recover the congestion map by exploiting several upsampling layers and merging with EFF features. Compared with the existing state-of-the-art congestion prediction models, experimental results demonstrate that our model not only outperforms them in prediction accuracy, but also excels in reducing routing congestion when integrated into the placer DREAMPlace.

Field-programmable gate array (FPGA) macro placement holds a crucial role within the FPGA physical design flow since it substantially influences the subsequent stages of cell placement and routing. In this paper, we propose an effective and efficient routability-driven macro placement algorithm for modern FPGAs with cascade shape and region constraints. To reserve adequate space for cell placement and guarantee routability, we first develop a routability-driven mixed-size analytical global placement (GP) that evenly distributes both macros and cells while considering cascade shape and region constraints. Then, we propose an integer linear programming (ILP)-based cascade shape legalization (LG) followed by matching-based macro legalization to remove macro overlaps while satisfying the region constraints. Finally, a routability-driven detailed macro placement is proposed to refine the solution. Compared with the top contestants of the MLCAD 2023 contest, experimental results show that our algorithm achieves the best overall score and routability.

Macro placement is a crucial and complex task in chip design. In recent years, reinforcement learning (RL) has emerged as a promising approach for autonomously generating effective macro placement on a grid-based chip canvas. However, existing RL-based macro placers encounter challenges when handling macros of varying sizes and preplaced blocks, due to using coarse-grained grids leads to wastage of placement space, while employing fine-grained grids results in an exponentially growing solution space and significant computational overhead. This brief proposes a legalization-aided RL-based macro placement (LAMPlace) for mixed-size designs with preplaced blocks. LAMPlace leverages RL to generate a global macro placement that allows possible overlap, followed by a macro legalization algorithm to ensure the legality of macro placement. LAMPlace can effectively address macros of various sizes and preplaced blocks because the action mask generation algorithm in RL is well coupled with the macro legalization algorithm. Compared with the state-of-the-art works, experimental results on publicly mixed-size placement benchmarks show that LAMPlace is effective.

In this paper, we propose a few-shot indoor position method based on Triplet Matchnet, which transforms coordinate positioning into channel state information (CSI) similarity matching problem. Triplet loss is designed to train and learn hidden correspondence between CSI features and physical space positions, with emphasis on minimizing distance or angle-based triplet loss. Then, according to pre-trained network with best similarity match, a similarity score map of CSI with unknown coordinates is constructed to predict position precisely. Experimental results show that angle-based triplet loss can obtain more accurate CSI fingerprint similarity matching accuracy. Compared with existing methods, experiment results confirm that our proposed method can achieve excellent positioning performance with few-shot datasets.