Jongkil Park

A deep understanding of neuronal circuitry connectivity is essential to replicate biological functions effectively. Inferring neural connectivity considers the cross-correlation of spike timing. Neuromorphic systems utilize online learning algorithms that leverage the temporal correlations of spikes by utilizing spiking neural networks. This research demonstrates real-time, large-scale neural connectivity inference by implementing the presynaptic spike-driven spike-timing-dependent plasticity method on neuromorphic hardware. We validate the capability of the proposed method to perform advanced neuron connectivity inference using synthetic data generated from leaky integrate-and-fire neurons on a multi-scale. Additionally, we analyzed that the proposed method exhibits invariant high inference performance in sparse networks without burst firing, regardless of transmission delay. Finally, we demonstrate the feasibility of the proposed method in real-time neural connectivity inference in actual in vitro or in vivo contexts by conducting neural connectivity inference simulating in a way closely mirroring in vitro conditions through fluorescence imaging signal data.

Spiking neural networks, known for mimicking the brain’s functionality resulting in efficient algorithms, are gaining attention across various problems and applications. However, their potential in regression tasks remains relatively unexplored. This study focuses on leveraging the spiking neural architecture in conjunction with Fourier analysis and support vector regression to estimate heart rates from electrocardiogram signal. We evaluated the regression errors of our model using three distinct elctrocardiogram datasets and assessed its performance on neuromorphic hardware by embedding spike-based layers. Our findings reveal that, compared to the conventional deep learning models, the proposed spiking neural system achieves a computational efficiency improvement while maintaining the competitive regression accuracy. Finally, we discuss the regression performance, energy efficiency, biological plausibility, and potential applications of the proposed neuromorphic system.

Neuromorphic cognitive computing offers a bio-inspired means to approach the natural intelligence of biological neural systems in silicon integrated circuits. Typically, such circuits either reproduce biophysical neuronal dynamics in great detail as tools for computational neuroscience, or abstract away the biology by simplifying the functional forms of neural computation in large-scale systems for machine intelligence with high integration density and energy efficiency. Here we report a hybrid which offers biophysical realism in the emulation of multi-compartmental neuronal network dynamics at very large scale with high implementation efficiency, and yet with high flexibility in configuring the functional form and the network topology. The integrate-and-fire array transceiver (IFAT) chip emulates the continuous-time analog membrane dynamics of 65 k two-compartment neurons with conductance-based synapses. Fired action potentials are registered as address-event encoded output spikes, while the four types of synapses coupling to each neuron are activated by address-event decoded input spikes for fully reconfigurable synaptic connectivity, facilitating virtual wiring as implemented by routing address-event spikes externally through synaptic routing table. Peak conductance strength of synapse activation specified by the address-event input spans three decades of dynamic range, digitally controlled by pulse width and amplitude modulation (PWAM) of the drive voltage activating the log-domain linear synapse circuit. Two nested levels of micro-pipelining in the IFAT architecture improve both throughput and efficiency of synaptic input. This two-tier micro-pipelining results in a measured sustained peak throughput of 73 Mspikes/s and overall chip-level energy efficiency of 22 pJ/spike. Non-uniformity in digitally encoded synapse strength due to analog mismatch is mitigated through single-point digital offset calibration. Combined with the flexibly layered and recurrent synaptic connectivity provided by hierarchical address-event routing of registered spike events through external memory, the IFAT lends itself to efficient large-scale emulation of general biophysical spiking neural networks, as well as rate-based mapping of rectified linear unit (ReLU) neural activations.

A spiking neural network (SNN) is a type of artificial neural network that operates based on discrete spikes to process timing information, similar to the manner in which the human brain processes real-world problems. In this paper, we propose a new spiking neural network (SNN) based on conventional, biologically plausible paradigms, such as the leaky integrate-and-fire model, spike timing-dependent plasticity, and the adaptive spiking threshold, by suggesting new biological models; that is, dynamic inhibition weight change, a synaptic wiring method, and Bayesian inference. The proposed network is designed for image recognition tasks, which are frequently used to evaluate the performance of conventional deep neural networks. To manifest the bio-realistic neural architecture, the learning is unsupervised, and the inhibition weight is dynamically changed; this, in turn, affects the synaptic wiring method based on Hebbian learning and the neuronal population. In the inference phase, Bayesian inference successfully classifies the input digits by counting the spikes from the responding neurons. The experimental results demonstrate that the proposed biological model ensures a performance improvement compared with other biologically plausible SNN models.

This paper proposes a new clock offset estimation that mitigates unwanted link asymmetry for precise clock synchronization. The main contribution is to address the primary and traditional design issue of the IEEE 1588 standard precision time protocol (PTP), which estimates clock offset under the assumption that the delays of exchanged packets are symmetric. To mitigate the issue, we focus on the fact that PTP measures asymmetry variation through the derivatives of its timestamps with respect to the time step. By exploiting the measurement of the variation, the proposed approach defines the asymmetry in the form of a linear differential equation (LDE) and leverages the LDE to define and exclude asymmetry-induced errors. Additionally, we clearly derive the state transition of the asymmetry. Subsequently, we derive a novel state-space model from our approach. The model describes PTP clock offset estimation perfectly, allowing optimal clock offset estimation. We verify the theoretical validity of the proposed method with real data. Our approach improves PTP accuracy by more than thousand times and achieves an accuracy at the level of tens to hundreds of nanoseconds on an asymmetric communication link. Our approach realizes an accuracy comparable to that of PTPv2, without the cost of specialized hardware.

Recently, many large-scale neuromorphic systems that emulate spiking neural networks have been presented. Biological evidence emphasizes the importance of the log-normal distribution of biological neural and synaptic parameters in the brain; however, this fact is easily ignored sometimes, and the parameters are excessively optimized to scale up a system. This is because high-precision parameters require floating-point arithmetic $-$ an operation known to consume high-energy and result in a high implementation cost in digital hardware. In this study, we propose a novel neuron implementation model that enhances neural and synaptic dynamics using the time-embedded floating-point arithmetic for better biological plausibility and low-power consumption. The proposed algorithm enables sharing temporal information with a membrane potential by time-embedded floating-point arithmetic, thus minimizing the memory usage of the neural state. In addition, this method need not access the static random-access memory at every time step, thus reducing the dynamic power consumption, even with a floating-point precision neural and synaptic dynamics. Using the proposed model, we implemented a core group with a total of 8,192 neurons on a field-programmable gate array device, Xilinx XC7K160T. The core group is designed for use in large-scale neuromorphic systems. We tested the neuron model in a core under various experimental conditions.

In this paper, we propose a novel Poisson process generator that uses multiple thermal noise amplifiers (TNAs) as a source of randomness and controls its event rate via a frequency-locked loop (FLL). The increase in the number of TNAs extends the effective bandwidth of amplified thermal noise and hence enhances the maximum event rate the proposed architecture can generate. Verilog-A simulation of the proposed Poisson process generator shows that its maximum event rate can be increased by a factor of 26.5 when the number of TNAs increases from 1 to 10. In order to realize parallel stochastic simulations of the biochemical reaction network, we present a fundamental reaction building block with continuous-time multiplication and addition using an AND gate and a 1-bit current-steering digital-to-analog converter, respectively. Stochastic biochemical reactions consisting of the fundamental reaction building blocks are simulated in Verilog-A, demonstrating that the simulation results are consistent with those of conventional Gillespie algorithm. An increase in the number of TNAs to accelerate the Poisson events and the use of digital AND gates for robust reaction rate calculations allow for faster and more accurate stochastic simulations of biochemical reactions than previous parallel stochastic simulators.

Neuromorphic hardware is a system with massive potential to enable efficient computing by mimicking the human brain. The novel system processes information using neuron spikes (Action Potentials) and the synaptic connections between neurons are trained using biologically plausible methods like spike-timing-dependent plasticity (STDP). Memristor is one of the promising candidates to implement such neuromorphic hardware. Two types of memristors, diffusive and drift, have been proposed to form a synapse showing faithful emulation of STDP, where the diffusion effect is used to trace the spike timing history crucial for STDP and the drift memristor keeps the weight information in a longer time scale. The purpose of this paper is to systematically investigate STDP characteristics in such a synapse with serially connected two memristors using SPICE models. The results show that STDP properties are strongly dependent on device parameters and even the shape of STDP curves is modified. Different shapes of the STDP curve were identified. The results and analysis could support the design of emerging device-based synapses, which can faithfully mimic biological STDP characteristics for future neuromorphic systems.

A synaptic device that contains weight information between two neurons is one of the essential components in a neuromorphic system, which needs highly linear and symmetric characteristics of weight update. In this study, a charge trap flash (CTF) memory device with a multilayered high-κ barrier oxide structure on the MoS₂ channel is proposed. The fabricated device was oxide-engineered on the barrier oxide layers to achieve improved synaptic functions. A comparison study between two fabricated devices with different barrier oxide materials (Al₂O₃ and SiO₂) suggests that a high-κ barrier oxide structure improves the synaptic operations by demonstrating the increased on/off ratio and symmetry of synaptic weight updates due to a better coupling ratio. Lastly, the fabricated device has demonstrated reliable potentiation and depression behaviors and spike-timing-dependent plasticity (STDP) for use in a spiking neural network (SNN) neuromorphic system.