Jaewook Kim

A deep understanding of neuronal circuitry connectivity is essential to replicate biological functions effectively. Inferring neural connectivity considers the cross-correlation of spike timing. Neuromorphic systems utilize online learning algorithms that leverage the temporal correlations of spikes by utilizing spiking neural networks. This research demonstrates real-time, large-scale neural connectivity inference by implementing the presynaptic spike-driven spike-timing-dependent plasticity method on neuromorphic hardware. We validate the capability of the proposed method to perform advanced neuron connectivity inference using synthetic data generated from leaky integrate-and-fire neurons on a multi-scale. Additionally, we analyzed that the proposed method exhibits invariant high inference performance in sparse networks without burst firing, regardless of transmission delay. Finally, we demonstrate the feasibility of the proposed method in real-time neural connectivity inference in actual in vitro or in vivo contexts by conducting neural connectivity inference simulating in a way closely mirroring in vitro conditions through fluorescence imaging signal data.

Recently, many large-scale neuromorphic systems that emulate spiking neural networks have been presented. Biological evidence emphasizes the importance of the log-normal distribution of biological neural and synaptic parameters in the brain; however, this fact is easily ignored sometimes, and the parameters are excessively optimized to scale up a system. This is because high-precision parameters require floating-point arithmetic $-$ an operation known to consume high-energy and result in a high implementation cost in digital hardware. In this study, we propose a novel neuron implementation model that enhances neural and synaptic dynamics using the time-embedded floating-point arithmetic for better biological plausibility and low-power consumption. The proposed algorithm enables sharing temporal information with a membrane potential by time-embedded floating-point arithmetic, thus minimizing the memory usage of the neural state. In addition, this method need not access the static random-access memory at every time step, thus reducing the dynamic power consumption, even with a floating-point precision neural and synaptic dynamics. Using the proposed model, we implemented a core group with a total of 8,192 neurons on a field-programmable gate array device, Xilinx XC7K160T. The core group is designed for use in large-scale neuromorphic systems. We tested the neuron model in a core under various experimental conditions.

Neuromorphic hardware is a system with massive potential to enable efficient computing by mimicking the human brain. The novel system processes information using neuron spikes (Action Potentials) and the synaptic connections between neurons are trained using biologically plausible methods like spike-timing-dependent plasticity (STDP). Memristor is one of the promising candidates to implement such neuromorphic hardware. Two types of memristors, diffusive and drift, have been proposed to form a synapse showing faithful emulation of STDP, where the diffusion effect is used to trace the spike timing history crucial for STDP and the drift memristor keeps the weight information in a longer time scale. The purpose of this paper is to systematically investigate STDP characteristics in such a synapse with serially connected two memristors using SPICE models. The results show that STDP properties are strongly dependent on device parameters and even the shape of STDP curves is modified. Different shapes of the STDP curve were identified. The results and analysis could support the design of emerging device-based synapses, which can faithfully mimic biological STDP characteristics for future neuromorphic systems.