Ding-Yuan Chen
Research Subjects
Ding-Yuan Chen has a total of 43 co-authors. Here are the top co-authors by number of shared publications:
- Niklas Rorsman
Department of Microtechnology and Nanoscience, Chalmers University of Technology, Gothenburg, Sweden
6 shared publications - Mattias Thorsell
Department of Microtechnology and Nanoscience, Chalmers University of Technology, Gothenburg, Sweden
5 shared publications Jr-Tai Chen
SweGaN AB, Linkping, Sweden
4 shared publications- Jr-Tai Chen
SweGaN AB, Linköping, SWEDEN
3 shared publications Kai-Hsin Wen
SweGaN AB, Linkping, Sweden
3 shared publications- Axel R. Persson
Center for III-Nitride Technology, C3NiT-Janzen, Linköping University, Linköping, Sweden
2 shared publications
Latest Publications
- 21 April 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 72 (5) , 2252-2258
Current Collapse in Buffer-Free GaN-on-SiC Power Transistors: Maxwell-Wagner Effect and Related Model
Recently, the use of insulating substrates has emerged as a viable option for the fabrication of GaN power transistors exceeding 1 kV. Such structures are of interest because no doped buffer is used, so—ideally—a low dynamic RDSON is expected. This article investigates the recoverable (and temperature dependent) current lowering induced by negative backgating in buffer-free GaN-on-SiC devices. Remarkably, we demonstrate that such an effect is not directly related to charge trapping, but to the Maxwell–Wagner effect, i.e., the charge migration at the interface between the insulating SiC substrate and the semi-insulating GaN layer. Accordingly, a model is defined and validated to simulate with great accuracy, the current decreases (and related kinetics) as a function of temperature, voltage, and time.
- 21 April 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 72 (5) , 2252-2258
Current Collapse in Buffer-Free GaN-on-SiC Power Transistors: Maxwell-Wagner Effect and Related Model
Recently, the use of insulating substrates has emerged as a viable option for the fabrication of GaN power transistors exceeding 1 kV. Such structures are of interest because no doped buffer is used, so—ideally—a low dynamic RDSON is expected. This article investigates the recoverable (and temperature dependent) current lowering induced by negative backgating in buffer-free GaN-on-SiC devices. Remarkably, we demonstrate that such an effect is not directly related to charge trapping, but to the Maxwell–Wagner effect, i.e., the charge migration at the interface between the insulating SiC substrate and the semi-insulating GaN layer. Accordingly, a model is defined and validated to simulate with great accuracy, the current decreases (and related kinetics) as a function of temperature, voltage, and time.
- 3 May 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 71 (6) , 3596-3602
Characterization of Trapping Effects Related to Carbon Doping Level in AlGaN Back-Barriers for AlGaN/GaN HEMTs
The impact of different carbon concentrations in the Al0.06Ga0.94N graded back-barrier and GaN buffer of high electron mobility transistors (HEMTs) is investigated. Four epi-wafers with different carbon concentrations, ranging from $1\times 10^{{17}}$ to $5\times 10^{{17}}$ cm $^{-{3}}$ , were grown by metal organic chemical vapor deposition (MOCVD). HEMTs with 100 and 200 nm gate lengths were fabricated and characterized with dc, Pulsed-IV, drain current transient spectroscopy (DCTS), and large-signal measurements at 30 GHz. It is shown that the back-barrier effectively prevents buffer-related electron trapping. The highest C-doping provides the best 2DEG confinement, while lower carbon doping levels are beneficial for a high output power and efficiency. A C-doping of $1\times 10^{{17}}$ cm $^{-{3}}$ offers the highest output power at maximum power added efficiency (PAE) (1.8 W/mm), whereas $3\times 10^{{17}}$ cm $^{-{3}}$ doping provides the highest PAE (>40%). The C-profiles acquired by using secondary ion mass spectroscopy (SIMS), in combination with DCTS, is used to explain the electron trapping effects. Traps associated with the C-doping in the back-barrier are identified and the bias ranges for the trap activation are discussed. The study shows the importance of considering the C-doping level in the back-barrier of microwave GaN HEMTs for power amplification and generation.
- 3 May 2024
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 71 (6) , 3596-3602
Characterization of Trapping Effects Related to Carbon Doping Level in AlGaN Back-Barriers for AlGaN/GaN HEMTs
The impact of different carbon concentrations in the Al0.06Ga0.94N graded back-barrier and GaN buffer of high electron mobility transistors (HEMTs) is investigated. Four epi-wafers with different carbon concentrations, ranging from $1\times 10^{{17}}$ to $5\times 10^{{17}}$ cm $^{-{3}}$ , were grown by metal organic chemical vapor deposition (MOCVD). HEMTs with 100 and 200 nm gate lengths were fabricated and characterized with dc, Pulsed-IV, drain current transient spectroscopy (DCTS), and large-signal measurements at 30 GHz. It is shown that the back-barrier effectively prevents buffer-related electron trapping. The highest C-doping provides the best 2DEG confinement, while lower carbon doping levels are beneficial for a high output power and efficiency. A C-doping of $1\times 10^{{17}}$ cm $^{-{3}}$ offers the highest output power at maximum power added efficiency (PAE) (1.8 W/mm), whereas $3\times 10^{{17}}$ cm $^{-{3}}$ doping provides the highest PAE (>40%). The C-profiles acquired by using secondary ion mass spectroscopy (SIMS), in combination with DCTS, is used to explain the electron trapping effects. Traps associated with the C-doping in the back-barrier are identified and the bias ranges for the trap activation are discussed. The study shows the importance of considering the C-doping level in the back-barrier of microwave GaN HEMTs for power amplification and generation.
- 1 September 2023
- Published by IOP Publishing in Semiconductor Science and Technology
- Vol. 38 (10) , 105006
Structural investigation of ultra-low resistance deeply recessed sidewall ohmic contacts for AlGaN/GaN HEMTs based on Ti/Al/Ti-metallization
This study presents a novel approach to forming low-resistance ohmic contacts for AlGaN/GaN HEMTs. The optimized contacts exhibit an outstanding contact resistance of approximately 0.15 Ω·mm. This is achieved by firstly recessing the barrier of the heterostructure to a depth beyond the channel. In this way, the channel region is exposed on the sidewall of the recess. The coverage of the Ti/Al/Ti ohmic metalization on the sidewall is ensured through tilting of the sample during evaporation. The annealing process is performed at a low temperature of 550 °C. The approach does not require precise control of the recess etching. Furthermore, the method is directly applicable to most barrier designs in terms of thickness and Al-concentration. The impact of recessed sidewall angle, thickness and ratio of Ti and Al layers, and the annealing procedure are investigated. Structural and chemical analyses of the interface between the ohmic contacts and epi-structure indicate the formation of ohmic contacts by the extraction of nitrogen from the epi-structure. The approach is demonstrated on HEMT-structures with two different barrier designs in terms of Al-concentration and barrier thickness. The study demonstrate large process window in regard to recess depth and duration of the annealing as well as high uniformity of the contact resistance across the samples, rendering the approach highly suitable for industrial production processes.
- 1 September 2023
- Published by IOP Publishing in Semiconductor Science and Technology
- Vol. 38 (10) , 105006
Structural investigation of ultra-low resistance deeply recessed sidewall ohmic contacts for AlGaN/GaN HEMTs based on Ti/Al/Ti-metallization
This study presents a novel approach to forming low-resistance ohmic contacts for AlGaN/GaN HEMTs. The optimized contacts exhibit an outstanding contact resistance of approximately 0.15 Ω·mm. This is achieved by firstly recessing the barrier of the heterostructure to a depth beyond the channel. In this way, the channel region is exposed on the sidewall of the recess. The coverage of the Ti/Al/Ti ohmic metalization on the sidewall is ensured through tilting of the sample during evaporation. The annealing process is performed at a low temperature of 550 °C. The approach does not require precise control of the recess etching. Furthermore, the method is directly applicable to most barrier designs in terms of thickness and Al-concentration. The impact of recessed sidewall angle, thickness and ratio of Ti and Al layers, and the annealing procedure are investigated. Structural and chemical analyses of the interface between the ohmic contacts and epi-structure indicate the formation of ohmic contacts by the extraction of nitrogen from the epi-structure. The approach is demonstrated on HEMT-structures with two different barrier designs in terms of Al-concentration and barrier thickness. The study demonstrate large process window in regard to recess depth and duration of the annealing as well as high uniformity of the contact resistance across the samples, rendering the approach highly suitable for industrial production processes.
- Open Access
- 9 May 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 70 (6) , 3005-3010
Transconductance Overshoot, a New Trap-Related Effect in AlGaN/GaN HEMTs
DC characteristics of AlGaN/GaN HEMTs with different thickness values of the undoped GaN channel layer were compared. An abnormal transconductance ( ${g}_{m}{)}$ overshoot accompanied by a negative threshold voltage ( ${V}_{\text {TH}}{)}$ shift was observed during ${I}_{\text {DS}}$ – ${V}_{\text {GS}}$ sweep in devices with thinner GaN layer. At the same time, a non-monotonic increase in gate current was observed. In OFF-state, electron trapping occurs in the undoped GaN layer or at the GaN/AlN interface, leading to a positive ${V}_{\text {TH}}$ shift. When the device is turning on at a sufficiently high ${V}_{\text {DS}}$ , electron de-trapping occurs due to trap impact-ionization; consequently, ${V}_{\text {TH}}$ and therefore ${I}_{\text {D}}$ suddenly recovers, leading to the ${g}_{m}$ overshoot effect. These effects are attributed to electron trap impact-ionization and consequent modulation of the device’s electric field.
- 9 May 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 70 (6) , 3005-3010
Open AccessTransconductance Overshoot, a New Trap-Related Effect in AlGaN/GaN HEMTs
DC characteristics of AlGaN/GaN HEMTs with different thickness values of the undoped GaN channel layer were compared. An abnormal transconductance ( ${g}_{m}{)}$ overshoot accompanied by a negative threshold voltage ( ${V}_{\text {TH}}{)}$ shift was observed during ${I}_{\text {DS}}$ – ${V}_{\text {GS}}$ sweep in devices with thinner GaN layer. At the same time, a non-monotonic increase in gate current was observed. In OFF-state, electron trapping occurs in the undoped GaN layer or at the GaN/AlN interface, leading to a positive ${V}_{\text {TH}}$ shift. When the device is turning on at a sufficiently high ${V}_{\text {DS}}$ , electron de-trapping occurs due to trap impact-ionization; consequently, ${V}_{\text {TH}}$ and therefore ${I}_{\text {D}}$ suddenly recovers, leading to the ${g}_{m}$ overshoot effect. These effects are attributed to electron trap impact-ionization and consequent modulation of the device’s electric field.
- 3 November 2022
- Published by Wiley in Physica Status Solidi (a)
- Vol. 220 (16)
Impact of the Channel Thickness on Electron Confinement in MOCVD‐Grown High Breakdown Buffer‐Free AlGaN/GaN Heterostructures
The 2D electron gas (2DEG) confinement on high electron mobility transistor (HEMT) heterostructures with a thin undoped GaN channel layer on the top of a grain‐boundary‐free AlN nucleation layer is studied. This is the first time demonstration of a buffer‐free epi‐structure grown with metal–organic chemical vapor deposition with thin GaN channel thicknesses, ranging from 250 to 150 nm, without any degradation of the structural quality and 2DEG properties. The HEMTs with a gate length of 70 nm exhibit good DC characteristics with peak transconductances of 500 mS mm−1and maximum saturated drain currents above 1 A mm−1. A thinner GaN channel layer improves 2DEG confinement because of the enhanced effectiveness of the AlN nucleation layer acting as a back‐barrier. An excellent drain‐induced barrier lowering of only 20 mV V−1at aVDSof 25 V and an outstanding critical electric field of 0.95 MV cm−1are demonstrated. Good large‐signal performance at 28 GHz with output power levels of 2.0 and 3.2 W mm−1and associated power‐added efficiencies of 56% and 40% are obtained at aVDSof 15 and 25 V, respectively. These results demonstrate the potential of sub‐100 nm gate length HEMTs on a buffer‐free GaN‐on‐SiC heterostructure.
- 3 November 2022
- Published by Wiley in Physica Status Solidi (a)
- Vol. 220 (16)
Impact of the Channel Thickness on Electron Confinement in MOCVD‐Grown High Breakdown Buffer‐Free AlGaN/GaN Heterostructures
The 2D electron gas (2DEG) confinement on high electron mobility transistor (HEMT) heterostructures with a thin undoped GaN channel layer on the top of a grain‐boundary‐free AlN nucleation layer is studied. This is the first time demonstration of a buffer‐free epi‐structure grown with metal–organic chemical vapor deposition with thin GaN channel thicknesses, ranging from 250 to 150 nm, without any degradation of the structural quality and 2DEG properties. The HEMTs with a gate length of 70 nm exhibit good DC characteristics with peak transconductances of 500 mS mm−1and maximum saturated drain currents above 1 A mm−1. A thinner GaN channel layer improves 2DEG confinement because of the enhanced effectiveness of the AlN nucleation layer acting as a back‐barrier. An excellent drain‐induced barrier lowering of only 20 mV V−1at aVDSof 25 V and an outstanding critical electric field of 0.95 MV cm−1are demonstrated. Good large‐signal performance at 28 GHz with output power levels of 2.0 and 3.2 W mm−1and associated power‐added efficiencies of 56% and 40% are obtained at aVDSof 15 and 25 V, respectively. These results demonstrate the potential of sub‐100 nm gate length HEMTs on a buffer‐free GaN‐on‐SiC heterostructure.
- 25 January 2022
- Published by IOP Publishing in Semiconductor Science and Technology
- Vol. 37 (3) , 035011
Impact of in situ NH3 pre-treatment of LPCVD SiN passivation on GaN HEMT performance
The impact on the performance of GaN high electron mobility transistors (HEMTs) of in situ ammonia (NH3) pre-treatment prior to the deposition of silicon nitride (SiN) passivation with low-pressure chemical vapor deposition (LPCVD ) is investigated. Three different NH3 pre-treatment durations (0, 3, and 10 min) were compared in terms of interface properties and device performance. A reduction of oxygen (O) at the interface between SiN and epi-structure is detected by scanning transmission electron microscopy (STEM )-electron energy loss spectroscopy (EELS) measurements in the sample subjected to 10 min of pre-treatment. The samples subjected to NH3 pre-treatment show a reduced surface-related current dispersion of 9% (compared to 16% for the untreated sample), which is attributed to the reduction of O at the SiN/epi interface. Furthermore, NH3 pre-treatment for 10 min significantly improves the current dispersion uniformity from 14.5% to 1.9%. The reduced trapping effects result in a high output power of 3.4 W mm−1 at 3 GHz (compared to 2.6 W mm−1 for the untreated sample). These results demonstrate that the in situ NH3 pre-treatment before LPCVD of SiN passivation is critical and can effectively improves the large-signal microwave performance of GaN HEMTs.
- 25 January 2022
- Published by IOP Publishing in Semiconductor Science and Technology
- Vol. 37 (3) , 035011
Impact of in situ NH3 pre-treatment of LPCVD SiN passivation on GaN HEMT performance
The impact on the performance of GaN high electron mobility transistors (HEMTs) of in situ ammonia (NH3) pre-treatment prior to the deposition of silicon nitride (SiN) passivation with low-pressure chemical vapor deposition (LPCVD ) is investigated. Three different NH3 pre-treatment durations (0, 3, and 10 min) were compared in terms of interface properties and device performance. A reduction of oxygen (O) at the interface between SiN and epi-structure is detected by scanning transmission electron microscopy (STEM )-electron energy loss spectroscopy (EELS) measurements in the sample subjected to 10 min of pre-treatment. The samples subjected to NH3 pre-treatment show a reduced surface-related current dispersion of 9% (compared to 16% for the untreated sample), which is attributed to the reduction of O at the SiN/epi interface. Furthermore, NH3 pre-treatment for 10 min significantly improves the current dispersion uniformity from 14.5% to 1.9%. The reduced trapping effects result in a high output power of 3.4 W mm−1 at 3 GHz (compared to 2.6 W mm−1 for the untreated sample). These results demonstrate that the in situ NH3 pre-treatment before LPCVD of SiN passivation is critical and can effectively improves the large-signal microwave performance of GaN HEMTs.
- 15 April 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 41 (6) , 828-831
Microwave Performance of ‘Buffer-Free’ GaN-on-SiC High Electron Mobility Transistors
High performance microwave GaN-on-SiC HEMTs are demonstrated on a heterostructure without a conventional thick doped buffer. The HEMT is fabricated on a high-quality 0.25 μm unintentional doped GaN layer grown directly on a transmorphic epitaxially grown AlN nucleation layer. This approach allows the AlN-nucleation layer to act as a back-barrier, limiting short channel effects and removing buffer leakage. The devices with the ‘buffer-free’ heterostructure show competitive DC and RF characteristics, as benchmarked against the devices made on a commercial Fe-doped epi-wafer. Peak transconductances of 500 mS/mm and a maximum saturated drain current of ~1 A/mm are obtained. An extrinsic fT of 70 GHz and fmax of 130 GHz are achieved for transistors with a gate length of 100 nm. Pulsed-IV measurements reveal a lower current slump and a smaller knee walkout. The dynamic IV performance translates to an output power of 4.1 W/mm, as measured with active load-pull at 3 GHz. These devices suggest that the ‘bufferfree’ concept may offer an alternative route for high frequency GaN HEMTs with less electron trapping effects.
- 15 April 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 41 (6) , 828-831
Microwave Performance of ‘Buffer-Free’ GaN-on-SiC High Electron Mobility Transistors
High performance microwave GaN-on-SiC HEMTs are demonstrated on a heterostructure without a conventional thick doped buffer. The HEMT is fabricated on a high-quality 0.25 μm unintentional doped GaN layer grown directly on a transmorphic epitaxially grown AlN nucleation layer. This approach allows the AlN-nucleation layer to act as a back-barrier, limiting short channel effects and removing buffer leakage. The devices with the ‘buffer-free’ heterostructure show competitive DC and RF characteristics, as benchmarked against the devices made on a commercial Fe-doped epi-wafer. Peak transconductances of 500 mS/mm and a maximum saturated drain current of ~1 A/mm are obtained. An extrinsic fT of 70 GHz and fmax of 130 GHz are achieved for transistors with a gate length of 100 nm. Pulsed-IV measurements reveal a lower current slump and a smaller knee walkout. The dynamic IV performance translates to an output power of 4.1 W/mm, as measured with active load-pull at 3 GHz. These devices suggest that the ‘bufferfree’ concept may offer an alternative route for high frequency GaN HEMTs with less electron trapping effects.
- 10 April 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 67 (5) , 1952-1958
Electric-Based Thermal Characterization of GaN Technologies Affected by Trapping Effects
This article presents an electric-based methodology for thermal characterization of semiconductor technologies. It is shown that for technologies such as gallium nitride (GaN) high electron mobility transistors, which exhibit several field induced electron trapping effects, the thermal characterization has to be performed under specific conditions. The electric field is limited to low levels to avoid activation of trap states. At the same time, the dissipated power needs to be high enough to change the operating temperature of the device. The method is demonstrated on a test structure implemented as a GaN resistor with large contact separation. It is used to evaluate the thermal properties of samples with different silicon carbide suppliers and buffer thickness.
- 10 April 2020
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 67 (5) , 1952-1958
Electric-Based Thermal Characterization of GaN Technologies Affected by Trapping Effects
This article presents an electric-based methodology for thermal characterization of semiconductor technologies. It is shown that for technologies such as gallium nitride (GaN) high electron mobility transistors, which exhibit several field induced electron trapping effects, the thermal characterization has to be performed under specific conditions. The electric field is limited to low levels to avoid activation of trap states. At the same time, the dissipated power needs to be high enough to change the operating temperature of the device. The method is demonstrated on a test structure implemented as a GaN resistor with large contact separation. It is used to evaluate the thermal properties of samples with different silicon carbide suppliers and buffer thickness.
- 19 June 2006
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Journal of Lightwave Technology
- Vol. 24 (6) , 2340-2346
Analysis and design optimization of electrooptic interferometric modulators for microphotonics applications
Scaling the electrode layout (electrode gap, electrode length) down to microscale dimensions extends the application of electrooptic (EO) modulators to microphotonics. In this paper, design criteria are set up to minimize the switching voltage of microscale EO Mach-Zehnder interferometric modulators. Mach-Zehnder interferometric modulators under different directions of electric field with respect to the optic axis are analyzed. Three expressions of the intensity output characteristics are presented for various crystal classes and compared in terms of conditions of validity and design applications. The analysis in this paper suggests that the switching voltage is strongly related with the direction of the electric field relative to the optic axis. For the 4-mm BaTiO/sub 3/ (r/sub 33/=28 pm/V,r/sub 51/=820 pm/V) Mach-Zehnder modulators, r/sub 51/ is utilized when the electric field is applied normal to the optic axis. In this configuration, the thermal stability and polarization insensitivity improve but the extinction ratio becomes a function of the electrode length. The phase-retardation expression is useful to find a suitable modulator length and maximize the extinction ratio. Some of the discussions also apply to Fabry-Pe/spl acute/rot interferometric modulators.
- 19 June 2006
- Published by Institute of Electrical and Electronics Engineers (IEEE) in Journal of Lightwave Technology
- Vol. 24 (6) , 2340-2346
Analysis and design optimization of electrooptic interferometric modulators for microphotonics applications
Scaling the electrode layout (electrode gap, electrode length) down to microscale dimensions extends the application of electrooptic (EO) modulators to microphotonics. In this paper, design criteria are set up to minimize the switching voltage of microscale EO Mach-Zehnder interferometric modulators. Mach-Zehnder interferometric modulators under different directions of electric field with respect to the optic axis are analyzed. Three expressions of the intensity output characteristics are presented for various crystal classes and compared in terms of conditions of validity and design applications. The analysis in this paper suggests that the switching voltage is strongly related with the direction of the electric field relative to the optic axis. For the 4-mm BaTiO/sub 3/ (r/sub 33/=28 pm/V,r/sub 51/=820 pm/V) Mach-Zehnder modulators, r/sub 51/ is utilized when the electric field is applied normal to the optic axis. In this configuration, the thermal stability and polarization insensitivity improve but the extinction ratio becomes a function of the electrode length. The phase-retardation expression is useful to find a suitable modulator length and maximize the extinction ratio. Some of the discussions also apply to Fabry-Pe/spl acute/rot interferometric modulators.