Flavio Ponzina

The diffusion model has driven the advancement of Artificial Intelligence Generated Content (AIGC). The backbone of diffusion models is currently shifting from U-Net-based CNNs to Diffusion Transformers (DiTs) in order to achieve better generative quality and scalability. However, the inherent iterative computing paradigm of diffusion models, combined with the substantial computational demands of DiTs, poses significant challenges to processing latency. We identify significant multi-level spatial and temporal similarities in DiT execution, which we leverage to design AA-DiT, an algorithm-architecture co-designed accelerator that significantly speeds up the execution of DiT models by leveraging spatial and temporal similarities. We design a static/dynamic hybrid attention algorithm that detects and skips unnecessary computations based on the identified spatial similarities in the attention mechanism. Our algorithm also reuses the intermediate results from previous timesteps in both attention modules and Multilayer Perceptron (MLP) modules in DiT based on the identified temporal similarities. On the architecture side, we develop a cross-level design spanning circuit, dataflow, and scheduling levels. We first design the lightweight screening mechanism to coordinate with the static/dynamic hybrid attention’s runtime detection at low hardware cost. Second, we present the block-wise gathering dataflow to alleviate the irregular compute and memory access patterns caused by the hybrid attention algorithm. Third, we propose a reuse-aware scheduling method to efficiently support the cross-timestep intermediate result reuse. Through the synergistic integration of algorithm and architecture designs, our co-designed AA-DiT achieves up to 6.7× end-to-end speedup over the baselines, including the A100 GPU and state-of-the-art accelerators such as ViTCoD and Cambricon-D.

Hyperdimensional computing (HDC), a brain-inspired paradigm, encodes information as high-dimensional vectors and forms associations through bundling. Yet, the ability to selectively forget information—critical for privacy, security, and adaptability—remains unexplored in HDC. We show that unlearning in HDC is difficult due to its memorization nature: vectors are directly stored in associative memory and persist, making it hard to forget specific data, while naive removal causes severe accuracy loss. We propose ClearAttack, a Computationally light and effective unlearning framework for HDC. ClearAttack tracks the influence of encoded vectors and offsets the impact of forgotten data with suitable substitutes, enabling in situ unlearning. To further mitigate accuracy loss, it incorporates selective retraining on sensitive samples. Experimental results show that ClearAttack unlearns data more effectively and efficiently than prior methods, achieving up to 3.6× higher forget score, accuracy within 0.2–0.6% of the oracle model, and up to 5.2× faster execution. Moreover, ClearAttack successfully eliminates the effect of poisoned data, demonstrating its utility for both accuracy and security. Because the complete unlearning procedure costs a fraction of a single retraining epoch and adds only 6.4% memory overhead, deletion requests and poisoning recovery can be handled directly on resource-constrained devices rather than requiring a full retraining pass.

Real-world software–hardware co-design for AI accelerators must meet strict constraints on accuracy and PPA, making design space exploration both costly and inefficient. In this work, we define a metric-constrained multi-objective co-optimization problem and propose a constraint-scheduled Bayesian optimization framework, CSBO, that adapts constraint thresholds during the search. This scheduling balances exploration in early iterations with exploitation in later ones, improving both optimization efficiency and feasibility under metric constraints. Applied to HDnn-PIM, a state-of-the-art ML accelerator, our method increases feasible hypervolume and feasibility rate across datasets, while improving accuracy by 4.9%, energy by 287×, performance by 14×, and area by 2× compared to prior design through trade-offs.

Deploying Small Language Models (SLMs) on edge platforms is critical for real-time, privacy-sensitive generative AI, yet constrained by memory, latency, and energy budgets. Quantization reduces model size and cost but suffers from device noise in emerging non-volatile memories, while conventional memory hierarchies further limit efficiency. SRAM provides fast access but has low density, DRAM must simultaneously accommodate static weights and dynamic KV caches, which creates bandwidth contention, and Flash, although dense, is primarily used for initialization and remains inactive during inference. These limitations highlight the need for hybrid memory organizations tailored to LLM inference. We propose Outlier-aware Quantization with Memory Co-design (QMC), a retraining-free quantization with a novel heterogeneous memory architecture. QMC identifies inlier and outlier weights in SLMs, storing inlier weights in compact multi-level Resistive-RAM (ReRAM) while preserving critical outliers in high-precision on-chip Magnetoresistive-RAM (MRAM), mitigating noise-induced degradation. On language modeling and reasoning benchmarks, QMC outperforms and matches state-of-the-art quantization methods using advanced algorithms and hybrid data formats, while achieving greater compression under both algorithm-only evaluation and realistic deployment settings. Specifically, compared against SoTA quantization methods on the latest edge AI platform, QMC reduces memory usage by 6.3x-7.3x, external data transfers by 7.6x, energy by 11.7x, and latency by 12.5x when compared to FP16, establishing QMC as a scalable, deployment-ready co-design for efficient on-device inference.

Approximate Nearest-Neighbor Search (ANNS) is a key technique in retrieval-augmented generation (RAG), enabling rapid identification of the most relevant high-dimensional embeddings from massive vector databases. Modern ANNS engines accelerate this process using prebuilt indexes and store compressed vector-quantized representations in fast memory. However, they still rely on a costly second-pass refinement stage that reads full-precision vectors from slower storage like SSDs. For modern text and multimodal embeddings, these reads now dominate the latency of the entire query. We propose FaTRQ, a far-memory-aware refinement system using tiered memory that eliminates the need to fetch full vectors from storage. It introduces a progressive distance estimator that refines coarse scores using compact residuals streamed from far memory. Refinement stops early once a candidate is provably outside the top-k. To support this, we propose tiered residual quantization, which encodes residuals as ternary values stored efficiently in far memory. A custom accelerator is deployed in a CXL Type-2 device to perform low-latency refinement locally. Together, FaTRQ improves the storage efficiency by 2.4$\times$ and improves the throughput by up to 9$ \times$ than SOTA GPU ANNS system.