Zhihua Wang

With the increasing demand for large-scale model deployment, cloud-based computing remains indispensable. However, energy and bandwidth overheads in edge-to-cloud data transmission pose significant challenges. This work presents a low-power, multimodal SoC that performs on-chip image and audio compression processing, enabling energy-efficient and low-latency cloud interaction for Internet of Things (IoT) applications. The SoC employs a two-level optimization strategy. At the microarchitecture level, a customized 16-bit fixed-length complex instruction set computing (CISC) microprocessor is introduced. Validated against a RISC-V minimal baseline RV32E equipped with equivalent peripheral engines, the proposed core achieves a $5.06\times $ reduction in core logic gate count and up to $2.42\times $ improvement in energy efficiency under iso-latency conditions. Additionally, a multipower domain strategy is adopted to further optimize energy efficiency, yielding $5.03\times $ and $4.13\times $ improvements for image and audio modes, respectively. Fabricated in a 65-nm CMOS process, our SoC integrates both image and audio processing, achieving an ultralow power consumption of 54.1– $387.5~\mu $ W. It outperforms state-of-the-art dual-modal processors, achieving a $2.84\times $ reduction in image-processing core power and a $12.78\times $ reduction in audio compression power. Furthermore, our SoC achieves an energy efficiency of 206 pJ/bit of audio task and 15.5 pJ/pixel of image task, which offers a scalable and energy-efficient solution for versatile IoT deployments.

This article presents a cryogenic quantum interface chipset at 3.5 K for superconducting transmon qubit operations. The chipset comprises a phase-detection readout and a phase-shifter-based polar-modulation controller with flexible scalability. With the proposed phase-detection readout scheme, a 9-bit time-to-digital converter (TDC)-based state detector is used to read out the qubit state by detecting the phase difference between the stimulus signal and the reflected signal. A low-IF N-path filter-based receiver and a multi-tone transmitter are co-designed to enable frequency-division multiplexing (FDM) dispersive readout of multiple qubits. A phase-shifter-based polar-modulation XY-driver is developed with support for fast phase quantum gate operation and derivative-removal-by-adiabatic-gate (DRAG) pulse generation. The Z-driver is realized using a static digital-to-analog converter (DAC) array and a 10-bit dynamic DAC for power efficiency. Fabricated in a 28-nm bulk CMOS process, the chipset occupies a die area of 4.6 mm². The readout RX achieves a noise temperature of 40 K with a gain of 45–83 dB and a bandwidth of 1.2 GHz. The readout RX consumes 32% less power than state-of-the-art designs. The measured total readout power for simultaneous detection of two qubits is 12.2 mW, which is the lowest among readouts with a similar integration level. In addition, the controller achieves a spurious-free dynamic range (SFDR) of 49 dB for a 1-GS/s Z-driver and an SNR of 42 dB for a 1-GS/s XY-driver. The XY-driver consumes 4.3 mW per qubit under active control. Verified with practical transmon qubits, the readout fidelity exceeds 92.6%, approaching that of commercial instruments. A Rabi experiment at 5.61/6.36 MHz, a Ramsey experiment at 4.1 MHz, and a T1 experiment at $9.98~{\mu }$ s are also successfully observed using the proposed chipset at 3.5 K.

This letter presents a 12-bit 180-MS/s pipelined-SAR ADC in 65-nm CMOS. To eliminate the complex interstage gain-error calibration for fast-response characteristic, a high-gain residue amplifier (RA) featuring a 2-stage gain-boosting architecture is proposed. By removing the tail current, the RA significantly alleviates slew-rate and voltage headroom limitations. The pre-amplifier incorporates a polarity-aligned CMFB technique that minimizes Miller capacitance while implementing a non-inverting feedback loop, thereby eliminating the conventional auxiliary inverting amplifier. Furthermore, a hardware-efficient asynchronous SAR logic based on an improved 6-transistor TSPC-DFF is developed to reduce power and shorten logic path. The prototype ADC achieves 64.5-dB SNDR and 81-dB SFDR at Nyquist input, while consuming 3.7 mW from a 1.2-V supply.

This article presents a 2-element 18–50-GHz multiband phased-array transceiver supporting 5G frequency range 2 (FR2) bands (n257/n258/n259/n260/n261/n262) and FR2 nonterrestrial network (NTN) bands (n510/n511/n512). The design incorporates a frequency-reconfigurable power amplifier (PA) utilizing an asymmetric coupled multimode transformer and a triple-coupled frequency-reconfigurable network (TC-FRN), enabling band-shifting, bandwidth expansion, and spectrum reconstruction across 18–30 and 30–50 GHz. A tunable image-rejection filter (TIRF) is integrated into the TX path to enhance image-rejection capability and energy efficiency. In the receive path, a dual-path multiband low-noise amplifier (LNA) minimizes noise figure (NF) and power consumption while extending bandwidth. The phased-array transceiver employs a local oscillator (LO) phase-shifting architecture, incorporating a proposed distributed LO chain and an ultrawideband bidirectional mixer to reduce complexity and power consumption. The proposed transceiver is fabricated in a standard 65-nm bulk CMOS process. With the concerted efforts of all components, the transceiver can support complex modulated signals up to 64 QAM with a 400-Msys/s symbol rate from 18 to 50 GHz and maintain adjacent channel leakage ratio (ACLR) better than −30 dBc. The full path link performance is validated with 400-MHz 64-QAM signals and achieves error vector magnitude (EVM) results better than −25dB. The measured peak OP1dB is 16.7 dBm with 27.3-dB S21 at 28 GHz in the TX mode, and the minimum NF is 7.1dB with 35-dB S21 and −35.3-dBm IP1dB at 22 GHz in the RX mode. Benefiting from the TIRF and frequency-reconfigurable PA-LNA, an image-rejection ratio (IMRR) of 28.2-to-64.7 dBc can be achieved for the full path (TX-to-RX). Each element front end (FE) consumes DC power of 244 mW from 1 to 2 V in the TX and 53 mW in the RX, and the corresponding chip total power consumption is 434 and 337 mW.

The stability of a capacitor-less low-dropout regulator (LDO) is critical to the performance of the system on chips (SoCs). Because the dominant pole is typically load dependent, there is a stability challenge across the whole load current range, particularly at light-load current in capacitor-less LDOs design. To address this, a proposed capacitor-less LDO, which combines an adaptive zero compensation (AZC) methodology with a flipped voltage follower (FVF) loop, alleviates the stability issue and achieves fast transient response without extra quiescent current. Moreover, a negative capacitance circuit (NCC) is proposed to suppress the power supply noise coupling through the parasitic capacitance of the output power transistor and enhance the power supply rejection ratio (PSRR). The proposed capacitor-less LDO is implemented in a 180 nm standard CMOS process and occupies an active chip area of 0.0261 mm². The proposed AZC achieves a phase margin exceeding 45 degrees with the whole load-current from zero to 40 mA maximum load current. With a 36 μA minimum quiescent current, the experimental results show that the proposed LDO achieves a 0.5 ns transient response under a current step of 40 mAload with 2 ns edge time and a PSRR greater than-56 dB at 1 MHz. Good loop stability, transient responses and PSRR are achieved with a 0.45 ps and a 2.2 mV figure of merits (FOMs).