Woogeun Rhee

This article presents a 0.6-V high-efficiency Bluetooth low-energy (BLE) transmitter (TX) in 65-nm CMOS with following features: 1) a sub-mW hybrid phase-locked loop (PLL) for closed-loop modulation with a resistor digital-to-analog converter (RDAC)-based common-mode (CM) ripple cancellation to suppress reference spur; 2) a low-power switching current-source (SCS) digital/voltage-controlled oscillator (D/VCO) with a shared bias resistor for a differential varactor to cancel resistor noise; 3) a duty-cycle-controlled class-E/F₂ digital power amplifier (PA) to suppress third-harmonic distortion (HD3) without degrading PA efficiency; and 4) a calibration-free 1-bit $\Delta \Sigma $ high-pass modulation with finite-impulse response (FIR) filtering to overcome the nonlinearity issue of a low-voltage digitally controlled oscillator (DCO) in two-point modulation. The proposed TX implemented in 65-nm CMOS achieves a high system efficiency of 25.1% at 0-dBm output with closed-loop modulation. The reference spur level is reduced by more than 18 dB in both PLL and BLE spectrum. The TX exhibits second-harmonic distortion (HD2) and HD3 values of −50.1 and −52.1 dBm, respectively. The proposed TX satisfies BLE requirements while occupying a compact area of 0.46 mm² without external components.

This article presents an IEEE 802.15.4/4z ultrawideband (UWB) transceiver architecture that employs a finite-impulse response (FIR)-embedded quadrature hybrid correlation (QHC) method for low power and multipath mitigation. Like a rake receiver, the proposed analog correlator shifts a code instead of a UWB signal with FIR taps to relax the design complexity of an equalizer in the analog correlation. As a result, the power consumption for each FIR tap is reduced by more than ten times. A least-square-error-based FIR algorithm is proposed for the multipath mitigation of a burst position modulation (BPM) signal. To validate the proposed FIR-embedded QHC method, an 8-GHz 1T2R transceiver is implemented in 65-nm CMOS. The transceiver supports synchronization, BPM at 0.98/7.8 Mbaud/s, and precise localization. The receiver achieves −102-dBm sensitivity and consumes 12.2 mW/channel, while the FIR circuits consume 5.3% only. The chip supports localization with an rms time-of-arrival (ToA) error of 1.5 cm and an rms angle-of-arrival (AoA) error of 3.8°. With the duty-cycled operation, the transceiver consumes 27.9 mW at 0.98 Mbaud/s in the payload field and features the lowest power consumption among HRP-capable UWB transceivers.

This article describes a polar phase-tracking receiver (PT-RX) architecture that can work with various modulations including differential phase shift keying (DPSK), amplitude phase shift keying (APSK), and quadrature amplitude modulation (QAM). By employing a two-point injection method in a wideband digital phase-locked loop (DPLL), the proposed polar PT-RX performs various demodulations without requiring quadrature signal generation or a multi-bit analog-to-digital converter (ADC). Compared with existing PT-RXs, the proposed architecture not only overcomes the trade-off between frequency pulling and image rejection but also provides the equivalent constant gain of a digitally controlled oscillator (DCO) for robust demodulation. A prototype 5.8-mW 2.4-GHz polar PT-RX is implemented in 65-nm CMOS and performs demodulations of 8-DPSK at 1.5 Mb/s, 16-QAM at 2 Mb/s and 32-APSK at 2.5 Mb/s, achieving a sensitivity of −81, - 68, and −64 dBm, respectively.

This brief describes an ultra-wideband (UWB) transceiver architecture that employs a frequency-hopping code-division multiple-access (FH-CDMA) scheme for secure multi-sensor connectivity with up to 18-channel capacity. By using distinct frequency-hopping (FH) patterns based on m-sequence, quantitative analysis and simulation results show that the FH-CDMA UWB system can support up to 18 users simultaneously sharing the same transmission band. The duty cycle control of a carrier signal for each FH cycle enables the transmitter to perform baseband clock synchronization with nano-second resolution. A prototype 7.5-GHz UWB transceiver is implemented in 65-nm CMOS. With the FH enabled, the transmitter meets the UWB spectrum mask. The receiver achieves a sensitivity of –91 dBm at 25 kb/s and exhibits <1-dB degradation when three users transmit signals simultaneously.

This article presents an ultra-low voltage (ULV) fractional- $N$ hybrid phase-locked loop (PLL) without requiring bias current. A time-interleaved flip-flop phase detector (TI-FFPD) with duty-cycle-based phase detection is employed to achieve high linearity and low reference spur. A passive-intensive voltage-mode phase interpolator (VPI) with a supply-immune voltage scaling topology is proposed for $\Delta\Sigma$ quantization noise (Q-noise) reduction without gain or linearity calibration. A hybrid PLL (HPLL) that consists of a pseudo-differential analog proportional path and a digital integral path is implemented in 28-nm CMOS. The HPLL exhibits 607-fs $_{\mathrm{rms}}$ jitter and $-$ 59-dBc in-band fractional spur at 2.42-GHz output and consumes 0.78-mW power from a 0.5-V supply, achieving the best figure of merit (FoM $_{\mathrm{JIT}}$ ) of $-$ 245.4 dB among low-voltage ( $V_{\mathrm{DD}}$ $<$ 0.8 V) fractional- $N$ PLLs.