John Vista

This research article proposes a floating memristor emulator configuration based on n-type MOSFETs only. The proposed memristor comprises three nMOS and an extra nMOS for an external grounded capacitor. Compared to the existing literature, the proposed floating MOS memristor enables a simple design without any sophisticated design complexity. The actual fingerprint of the memristor as a pinched hysteresis loop with different frequency domains and composite characteristics as incremental and decremental are well examined using computer simulation with 90-nm CMOS technology parameters for MOSFETs. The power consumed by the proposed circuit is $2.6~\mu \text{W}$ . In addition, an experimental test using off-the-shelf components is investigated to verify the theoretical and simulated results. Moreover, the proposed nMOS-memristor emulator application is suitable for the modulation and demodulation of binary frequency-shift keying (BFSK) and Boolean logic gates.

This research article offers a floating Memristor model using single Voltage Difference Transconductance Amplifier (VDTA) and grounded passive components. The proper utilization of VDTA port characteristics with passive components exhibits both incremental and decremental modes of operation without multiplier circuit. The performance analysis of proposed memristor is verified by using post layout Cadence Virtuoso simulation to examine the characteristics of all possible temperature and process Corners. In addition, experimental verification of VDTA based Memristor is done using commercially available Operational Transconductance Amplifier (OTA) as IC CA3080. The results obtained through simulation and experiment follows the theoretical aspects. Moreover, an application perspective of the proposed design includes a brief neuromorphic circuit implementation for Pavlovian associative learning experiment.