Ankur Singh

Read-only memory (ROM) provides deterministic access to predefined data mappings. Extending ROM concepts to the optical domain enables high-bandwidth, low-latency, and parallel memory access, but realising compact, function-selectable optical ROM remains challenging due to loss, wavelength control, and integration constraints. This work presents a high-speed, function-selectable photonic ROM architecture implemented using integrated microring resonators (MRRs). The ROM encodes predefined input–output mappings directly in the spectral response of the photonic devices, enabling deterministic lookup-based operation without dynamic computation during readout. To improve scalability and reduce cumulative insertion loss, the architecture employs compact banked sub-arrays that are selectively addressed through an optical decoding mechanism. Run-time function selection is achieved using transistor-based optical selectors, allowing different ROM banks to be activated without physical light rerouting or interferometric structures. The proposed photonic ROM is designed and evaluated using device-level simulations based on the GlobalFoundries 45SPCLO silicon photonics platform. Simulation results support an access rate of 12.5 Gaccess/s with a maximum settling time of 31.3 ps, with stable light-to-current transfer characteristics obtained through integrated photodiode readout. The optical ROM can be used to implement nonlinear activation functions utilised in photonic accelerator architectures, including sigmoid, tanh, ReLU, and exponential mappings. In this use case, the ROM operates as a lookup table that stores predefined nonlinear transfer characteristics, demonstrating that complex nonlinear behaviours can be realised through static optical responses rather than active photonic computation. The use of activation functions in this work serves to illustrate the flexibility of the proposed ROM framework and does not constrain its general applicability to other lookup-based functions.

With the rapid growth of deep neural networks (DNNs), compute-in-memory (CIM) has emerged as a promising energy-efficient paradigm for accelerating multiply-and-accumulate (MAC) operations. Yet, current CIM architectures are largely limited to dot-product computations and struggle to efficiently support general-purpose matrix operations, such as transpose, element-wise addition, and multiplication. This work presents a 3D-integrated, memory-on-memory SRAM-eDRAM hybrid CIM architecture, implemented in GlobalFoundries 22 nm FDSOI technology, capable of performing general matrix operations directly within the memory crossbar with 4-bit precision. By leveraging a specialized transpose-based architecture, in-memory arithmetic operations, peripheral-aware design, and 3D SRAM–eDRAM integration, the proposed architecture balances latency, energy efficiency, and compute density for general purpose matrix operations while remaining compatible with the conventional CIM dot product architectures. Overall, this memory-on-memory CIM framework generalizes CIM beyond dot products, enabling versatile matrix processing and paving the way for broader applications in AI acceleration and general-purpose high performance computing.

Near-tissue computing requires sensor-level processing of high-resolution images, essential for real-time biomedical diagnostics and surgical guidance. We introduce a novel Capacitive Transimpedance Amplifier-based In-Pixel Computing (CTIA-IPC) architecture to address this need. Our design leverages CTIA pixels that are widely used for biomedical imaging owing to the inherent advantages of excellent linearity, low noise, and robust operation under low-light conditions. We augment CTIA pixels with IPC to enable multi-channel, multi-bit convolution operations along with integrated batch normalization (BN) and Rectified Linear Unit (ReLU) functionalities in the peripheral Analog to Digital Converter (ADC). Leveraging 3D integration to embed pixel circuitry and weight storage, CTIA-IPC maintains pixel density comparable to standard CTIA designs. Moreover, our algorithm-circuit co-design optimization results in minimal accuracy drop while providing significant data bandwidth reduction. Evaluated on the EndoVis tissue dataset (1280×1024), CTIA-IPC achieves approximately 12× reduction in data bandwidth, yielding segmentation IoUs of 75.93% (parts), and 28.60% (instrument), a minimal accuracy reduction (∼1.3%–2.5%) compared to baseline methods. Achieving 1.98 GOPS throughput and 3.39 GOPS/W efficiency, our CTIA-IPC architecture offers a promising computational framework tailored specifically for biomedical near-tissue computing.

Content-Addressable Memory (CAM) circuits enable inherently parallel and high-speed search operations, making them essential for data-intensive applications, such as packet classification in high-speed networking, pattern recognition, and artificial intelligence. However, as CMOS technology continues to scale, conventional electrical CAMs suffer from increasing interconnect delays, hindering their performance and energy efficiency in large-scale deployments. In contrast, photonic systems leverage light as the information carrier, offering ultra-fast data transmission with minimal signal degradation due to their length-independent impedance characteristics. In this work, we introduce OptiCAM—an optical CAM architecture that employs silicon photonic microring resonators and photodiode-based latch structures to store data and execute matching entirely in the optical domain. Furthermore, we present a novel sectioned array architecture that provides a pathway to build scalable CAM arrays, effectively overcoming the wavelength limitations imposed by the microring resonators’ free spectral range. Our OptiCAM design, evaluated on a 16 × 16 photonic CAM array using the commercial GlobalFoundries’ 45SPCLO technology node, achieves a remarkable search latency of 100 ps and an energy consumption of 100.9 fJ/bit per search.

Data‐intensive computing tasks, such as training neural networks, are fundamental to artificial intelligence applications but often demand substantial energy resources. This study presents a novel complementary metal‐oxide‐semiconductor (CMOS)‐based memcapacitor framework designed to address these challenges by enabling efficient and robust neuromorphic computing. Utilizing memcapacitor devices, a crossbar array that performs parallel vector‐matrix multiplication operations, validated through cadence simulations and implemented in python for scalable accelerator design, is developed. The framework demonstrates outstanding performance across classification tasks, achieving 98.4% accuracy in digit recognition and 85.9% in object recognition. A key aspect of this research is its focus on real‐world fabrication nonidealities, including up to 30% device parameter variations, ensuring robustness and reliability under practical deployment conditions. The results emphasize the effectiveness of capacitance‐based systems in handling classification tasks while demonstrating resilience to fabrication‐induced variations. This work establishes a foundation for scalable, energy‐efficient, and robust memcapacitor‐based neural networks, advancing the potential for intelligent systems in artificial intelligence‐driven applications and paving the way for future innovations in neuromorphic computing.

This study describes a VDBA (Voltage Differencing Buffered Amplifier)-based memristor emulator and its use in an instrumentation amplifier for biomedical applications. The proposed grounded and floating memristor has been implemented using a single VDBA and grounded MOS-Capacitor. The VDBA used in this article has also been designed and uses eighteen transistors only. The proposed memristor emulator can be operated in both decremental and incremental modes. The suggested emulator's robustness has been verified using a variety of evaluations, including non-ideal inspection, variations of process corner, temperature swings, and non-volatility performance. Using 45nm CMOS process parameters in the Cadence environment, the layout has been accomplished, and simulations and observations of the theoretical fingerprint characteristics have been made. The incremental and decremental mode of operation for grounded/floating memristor can be easily obtained by modifying the circuit slightly. The shape of the pinched-hysteresis loop is maintained up to 5MHz. The functionality of the proposed memristor has also been tested by integrating it with the Instrumentation amplifier to amplify weak bio-medical signals.

This research introduces a high-frequency CMOS meminductor, utilizing operational transconductance amplifiers and two grounded capacitors, thereby avoiding traditional components such as memristors, multipliers, and resistors. The design stands out for its simplicity and electronic adjustability, which facilitates control of the induced flux by altering the transconductance gain. We conducted transistor-level simulations with 180 nm CMOS technology to evaluate the meminductor’s performance across various parameters including voltage, frequency, temperature, process corner variations, and monte carlo simulations. These extensive tests confirm the durability and adaptability of the emulator across diverse conditions. The emulators operate up to 20 MHz with a remarkably low power consumption of just 0.44 mW, showcasing considerable efficiency. The practical applications of the proposed meminductor include advanced uses in developing leaky integrate and fire neuron. Additionally, we successfully fabricated the first physical meminductor emulator chip, which occupies a die area of $2032.7~\mu $ m2 using a 180 nm CMOS process. The integration of these fabrication results helps corroborate the theoretical derivations presented. This convergence of practical fabrication and theoretical insight signifies a major leap in meminductor technology, hinting at wide-ranging future applications in electronic systems.

In this paper, a multi-function embedded eye tracker system (ETS) has been presented and FPGA implementation of that has been described. The image processing algorithm is based on morphological operations to detect centers of pupil (PC) and corneal glint (GC) so that gaze of the user can be estimated by establishing a mapping between obtained PC-GC vector and screen. Moreover, the proposed ETS is capable to detect pupil size which is vitally important in understanding consciousness of the user since it varies in response to light condition. Taking advantage of optimum system design and parallel signal processing on high-speed digital units of the FPGA, the processing time of 1.8 ms was achieved that allows operation of the system up to 500 fps. The results of test with 176 × 120 images demonstrate maximum vertical or horizontal error of ±1 pixel. Experimental results imply versatility of the proposed low-power and high-accuracy ETS for real-time and accurate applications such as medical diagnosis and human-computer interface.