Peter Baumgartner

The impedance matching between power amplifier and antenna remains a challenge in millimeter-band front ends, particularly when the antenna impedance varies due to the use of beamforming. This article presents a tunable impedance matching filter fabricated in a 16-nm CMOS process. The frequency of operation is 77 GHz, making it suitable for millimeter-wave systems such as radar, Wi-Fi, and mobile communications. The filter is implemented using tunable quarter wavelength transmission lines. A reliability assessment supports that input powers up to 21 dBm can be used without risk. The on-wafer measurements demonstrate the functionality of the filter, which can adapt load impedances with a reflection coefficient $\Gamma$ of up to 0.37 and convert them down to less than 0.20, while keeping the source match also below 0.20 and the loss under 5.5 dB. Measurements across the wafer also show low process variability.

The selection of the appropriate technology is a key problem for millimeter-wave (mmW) circuits, especially for power amplifiers (PAs), due to the stringent power and efficiency requirements, reliability limitations, and cost considerations. This is particularly problematic in the case of complementary metal-oxide-semiconductor (CMOS) processes, which operate close to their limit in this kind of application. Technology choices are typically made based on the radio frequency (RF) figures of merit (FoMs) of the transistors or the quality factor of the inductors, which provide only limited insights into the performance of the target circuit. This article proposes a systematic design methodology based on two circuit-specific metrics, namely the PA FoM from the International Technology Roadmap for Semiconductors (ITRS) for the amplifying stages and the transducer power gain for the matching networks (MNWs). The methodology is demonstrated for a simple circuit architecture based on neutralized differential pairs (NDPs) and transformer-based MNWs. As a proof of concept, a three-stage fully differential $E$ -band PA prototype in a 16-nm FinFET process is designed, fabricated, and characterized. The prototype achieves a saturated output power of 15.2 dBm, small-signal gain of 34.9 dB, and power-added efficiency (PAE) of 30.3% at 70 GHz, which is a competitive performance with previous art in the $E$ -band in FinFET technologies.

The gate resistance is a parasitic element in transistors for RF and millimeter-wave circuits that can negatively impact power gain and noise figure. To develop accurate device models, a reliable measurement methodology is crucial. This article reviews the standard measurement methodology used in the literature and proposes also an additional method, which is evaluated using suitable test structures in a 16 nm FinFET process. The advantages and disadvantages of the two approaches are discussed along with their respective application scenarios.

For on-chip oscillator phase noise characterization and monitoring a common technique is the measurement of the equivalent cycle-to-cycle jitter. In this letter we show that the quantization introduced to the recorded jitter by the measurement with a time-to-digital converter can be prohibitive for calculating the phase noise, especially at high oscillation frequencies and for spectrally pure oscillators. A second drawback of this method is that supply voltage noise can mask the phase noise due to intrinsic device noise. To avoid these limitations, we investigate an approach where the oscillator under test is compared to an identical replica. The resulting time difference measurements are introduced as delta jitter. The validity of the method is proven in simulation and measurement of an on-chip jitter measurement macro designed in 16 nm FinFET CMOS technology. The measurement results indicate both robustness against quantization error and a self-canceling of correlated influences on phase noise in delta jitter measurements.

The gate resistance is a parasitic element in transistors for RF and millimeter-wave circuits that can negatively impact power gain and noise figure. To develop accurate device models, a reliable measurement methodology is crucial. This article reviews the standard measurement methodology used in the literature and proposes also an additional method, which is evaluated using suitable test structures in a 16nm FinFET process. The advantages and disadvantages of the two approaches are discussed along with their respective application scenarios

Recently emerging applications in the millimeter-wave (mm-wave) frequency range, such as automotive radar, satellite communications, 5G, 6G, and beyond, have brought new and significant challenges to the implementation of microwave circuits and systems. Many of these, such as speed, power consumption, signal-handling capability, linearity, integration possibilities, and cost, are directly related to the choice of the semiconductor process technology. For the implementation of a sophisticated mm-wave front end, different technology options are available, mainly the group III–V semiconductors, silicon–germanium (SiGe) heterojunction bipolar transistor/bipolar CMOS (BiCMOS), or CMOS processes in their multiple variants [1] – [3] .

This article presents a method for modeling high-Q resonant-fin transistors with focus on circuit design simulations. The model is implemented for simulations in a SPICE-like design environment and is based on two basic properties of the resonator device: the mechanical spectral behavior and the electro-mechanical-transfer function. The spectral model operates in the mechanical pressure regime, while the mobility model converts this pressure into a mobility change inside the channel of the transistor and is hence, generating an ac current at the output of the device. The model also includes the electrical transistor characteristic for the input and the output of the resonator. This enables accurate and fast circuit simulations with a standard SPICE simulator, e.g., for the design of frequency synthesizer circuits. The model is validated against finite element method (FEM) simulations at an artificially damped quality factor of Q= 500. Also, simulation results for a quality factor of Q = 50,000 are shown, to prove the full functionality of the electrical model.