Ji-Hwan Seol

We propose a fully integrated low-power keyword spotting (KWS) system on chip (SoC) with content-adaptive frame subsampling, implemented in 28-nm CMOS technology. The system is co-optimized from end-to-end including the analog frontend (AFE) and digital backend with a skip-recurrent neural network (RNN) KWS algorithm. The SoC performs dynamic power gating based on the decision from the skip-RNN algorithm that allows opportunistic frame skipping to reduce the power consumption without compromising the KWS accuracy. The design employs a fast-stabilizing AFE, enabling fast off to on transitions with a settling time of less than 1 ms. A low-power feature extractor (FE) and RNN classifier sprint with a relatively fast clock to minimize the latency of the frame-skipping decision and to minimize the leakage power overhead. The SoC integrates a custom-designed latch-based always-on on-chip memory to reduce leakage power to store all RNN weights on the chip. The proposed system achieves 1.48 $\mu$ W with an average of 76% skip ratio across frames, achieving 92.8% accuracy on a 7-class subset of the GSCD dataset. This work represents a significant step toward a low-power KWS SoC with content-adaptive frame subsampling for energy-efficient, deep-learning-enabled Internet-of-Things (IoT) devices.

This article describes an ultralow-power (ULP) temperature-compensated crystal oscillator (TCXO) with a pulsed-injection XO driver for IoT applications. Temperature compensation is achieved by changing the load capacitance ( ${C}_{L}$ ) between two values using a delta-sigma modulator ( $\Delta \Sigma \text{M}$ ). The complex modulation profile across temperature is approximated as piecewise linear elements that is selected by a coarse temperature sensor. As a result, the power and area of fine-grain look-up tables (LUTs) or a polynomial engine used in prior works can be avoided. The proposed pulsed-injection XO driver that directly replenishes the energy of the ${C}_{L}$ sustains the XO oscillation for the two different ${C}_{L}$ states. Implemented in 40-nm CMOS, the proposed 32.768-kHz TCXO achieves an accuracy of ±4.2 ppm from −20 °C to 85 °C with just three-point trimming and an Allan deviation floor of 34 ppb while consuming 43 nW, which is an approximate 8 $\times $ improvement over the recent state-of-the-art TCXOs.

This article presents a low jitter, low power, low reference spur LC oscillator-based reference oversampling digital phase locked loop (OSPLL). The proposed reference oversampling architecture simultaneously offers a low in-band phase noise, a wide-bandwidth, and a low spur. In addition, this article proposes an LC digitally controlled oscillator (DCO) for the proposed OSPLL to achieve a fast frequency update and fine frequency resolution, while its varactor switching timing is set optimally for low jitter using the proposed DCO tuning pulse timing control scheme. The proposed OSPLL was fabricated in a 28-nm CMOS process. The integrated rms jitter of the PLL was measured at 67.1 fs for an output frequency of 4 GHz. The in-band phase noise of the PLL was −129.2 and −132.5 dBc/Hz at 1- and 5-MHz offset frequencies. The measured reference spur of the PLL was −78.1 dBc. Total PLL power consumption was 5.2 mW, resulting in −256.3-dB PLL jitter-power FoM, while occupying 0.17-mm ² area.

An LC oscillator-based reference oversampling PLL (OSPLL) is proposed in this work. An LC digitally controlled oscillator (DCO) with proportional path gain profile control and DCO tuning pulse timing control scheme is proposed for optimal phase noise. Designed in 28nm CMOS process, the proposed PLL achieves 67.1fs RMS-jitter with 5.2mW power consumption, which translates to -256dB FoM. The in-band phase noise of the PLL is -130dBc/Hz at 4GHz output frequency. The reference spur of the proposed PLL is -78dBc.