Jaesuk Choi

This paper presents a comprehensive design tutorial for four types of single-stage operational transconductance amplifiers (OTAs): (1) five-transistor OTAs, (2) telescopic cascode OTAs, (3) folded cascode OTAs, and (4) current mirror OTAs. These OTAs serve as fundamental building blocks in analog circuits. The operational principles of each OTA are reviewed, and the key performance metrics are derived through a hand analysis. These performance metrics encompass most crucial parameters, including small-signal parameters, frequency response, input and output swing ranges, rising and falling slew rates, nonidealities, and bias circuit simplicity. All of these metrics are verified and compared using the simulation. Furthermore, the practical applications of each OTA are summarized, and a case study demonstrates the enhancement of a neural recording amplifier’s performance through appropriate OTA selection. A thorough review of the essential building blocks will become a stepping stone to design high-performance analog amplifiers across diverse applications.

This article presents an ultrasound (US) transceiver IC including a highly power-efficient US receiver (RX) and a high-voltage (HV) US transmitter (TX) for US capsule endoscopy (USCE) systems for the first time. The proposed USCE system employs the developed IC, a single-element piezoelectric transducer (PZT), and a mechanically rotating reflector to obtain 360 $^{\circ}$ transmural scans while traveling through the gastrointestinal (GI) tract. Since the USCE system operates with a tiny battery, power efficiency is greatly important. To reduce power consumption by decreasing the required operating speed of the analog-to-digital converter (ADC), we propose a new RX structure employing synchronized analog envelope detection. It is unlike conventional US RX ICs that necessitate power-hungry high-speed ADCs to acquire the US signal residing at a high center frequency with wide bandwidth. Instead, the proposed work employs an analog envelope detector based on a quadrature demodulation method. As a result, it uses only a single circuit path rather than two (I and Q) paths by using a demodulation carrier whose phase is synchronized with the incoming US signal. A ping-pong noise-shaping (NS) SAR ADC is adopted to improve resolution while maintaining low power consumption. Besides, the TX IC, including an on-chip charge pump, is designed to generate HV pulses to drive the PZT. The prototype IC is fabricated in a 0.18 $\mu$ m bipolar-CMOS-DMOS (BCD) process. The RX consumes 2.3 mW, and the ADC achieves a 53.71 dB SNDR and a 66.45 dB SFDR. The TX generates 25 V pulses with 25 ns pulsewidth. US B-mode images of a water tank and a custom phantom are successfully obtained by using the prototype capsule endoscopy system employing the fabricated IC chip.

This brief reviews high-voltage pulsers for ultrasound imaging systems with a focus on energy efficiency. Most ultrasound imaging systems have been developed with the aim of achieving a high signal-to-noise ratio for good image quality. As miniaturization and portability of the systems are pursued recently, high energy efficiency is of great need. In the ultrasonic imaging systems, the most power-hungry block is typically the pulser that drives the ultrasound transducer at a high voltage. To better understand the pulser’s operation and power consumption, an equivalent circuit model of the transducer is introduced. Based on the model, we investigate the fundamentals of pulser driving methods and review the conventional class-D pulser as well as state-of-the-art pulsers with dynamic power loss reduction techniques. Their operation principles, strengths, and limitations are analyzed and discussed in depth.

This paper presents a 5-bit VCO-based neural recording IC, which directly quantizes the input signal and achieves a large dynamic range (DR) to process the small-amplitude neural signal in the presence of the large-amplitude stimulation artifact (SA). A feedback-controlled source degeneration is applied to the input transconductor circuit (Gm,in) by using a resistor DAC (R-DAC). It mitigates the circuit nonlinearity, resulting in a large signal-to-noise-and-distortion ratio (SNDR) and a high input impedance (Z _in ). The implemented neural recording IC achieves 813dB SNDR over 200Hz signal bandwidth and 200mV _PP maximum allowable input range while consuming 3.9μW per channel.