Chul Kim

Wearable interfaces that capture both weak physiological fluctuations and large body motions remain difficult to realize in a single fiber because most strain‐sensing fibers are governed by one dominant electromechanical response mode. Consequently, mechanically distinct deformation regimes are ambiguously represented, limiting sensing range and information quality for downstream motion interpretation. Here, we develop a monolithic dual‐gradient fiber with complementary sensing regimes programmed through coupled materials and process design. By jointly tuning the percolation behavior and rheological drawability of carbon black/carbon nanotube‐filled styrene–ethylene–butylene–styrene (SEBS) composites, we identified two formulations suitable for coaxial co‐drawing within one continuous strand. The resulting fiber pairs a highly responsive layer for small deformation with a robust layer that stays informative at larger strain, producing synchronized but nonredundant signals. At low strain (0%–10%), the high‐sensitivity layer exhibits a gauge factor of 51.28, over four times the low‐sensitivity layer (12.42), while the two layers remain functional up to approximately 40% and 160% strain, respectively. This architecture preserves mechanically salient features across distinct and superimposed inputs, supporting measurements from pulse and respiration to joint motion. In a single‐fiber glove, the dual‐sensitivity design improves gesture‐classification accuracy by more than 10% relative to single‐sensitivity controls, enriching features for decoding.

The demand for high-throughput, multi-modal recording and stimulation in neuroscience research has driven the development of neural interfaces that optimize area and energy efficiency without compromising noise performance. Simultaneously, the need for on-chip data compression to reduce data volume has become increasingly critical. This work presents a neural interface system-on-chip (NISoC) that incorporates 1,024 channels for simultaneous electrical recording and stimulation, enabling high-resolution, high-throughput electrophysiology with record noise-energy efficiency. The 2 mm $\boldsymbol{\times}$ 2 mm NISoC, fabricated using 65 nm CMOS technology, integrates a 32 $\boldsymbol{\times}$ 32 array of electrodes vertically coupled to analog front-ends. These front-ends support both voltage and current clamping through a programmable interface, providing a voltage range up to 100 dB and a current range of 120 dB. Each channel operates at a power consumption of 0.81 $\mu$W, achieving an input-referred voltage noise of 8.8 $\mu V_{rms}$ over a signal bandwidth from DC to 12.5 kHz. The NISoC also integrates on-chip data acquisition through a back-end array of 32 dynamic incremental SAR ADCs, achieving 25 Msps and 11 effective number of bits (ENOB) acquisition with an energy efficiency of 2 fJ/level. The dynamic incremental SAR ADC architecture further offers additional functionality of intrinsic spike detection for future on-chip neural data compression.

Continuous neural signal acquisition during electrical stimulation is essential for neuromodulation; nevertheless, it is often hindered by high-amplitude stimulation artifacts (SAs). This study presents a neuromodulation system with an application-specific integrated circuit (ASIC) that implements 2.9$\times$ faster adaptation than a fixed parameter method for the real-time recovery of neural signals fully overlapped with stimulation artifacts in both time and frequency domains, without any prior calibration. The on-chip SA removal module leverages an adaptive infinite impulse response (IIR)-based template-subtraction method with zero-multiplier operation and low computational complexity, enabling rapid template convergence and high accuracy under time-varying SAs while optimizing area and power efficiency. The stimulator incorporates a stimulation frequency dithering mechanism to minimize neural signal loss at the stimulation frequency and its harmonics during recovery. In vitro and in vivo experimental validation, including local field potential (LFP) and action potential (AP) recordings, demonstrated real-time SA removal, achieving 40 dB reduction of SA component and preserving neural signal integrity. The ASIC, fabricated using the TSMC 65 nm CMOS LP process, occupies a total die area of 1 mm². The SA removal module including on-chip memory occupies 0.15 mm² and consumes 1.3 µW. The presented system enables recovery of neural signals obscured by time-varying SAs in real time, without requiring prior calibration or external processing units.

This article presents an enhanced-frequency-splitting-based wireless power and data transfer (EFS-WPDT) system that simultaneously delivers power and forward data over a compact inductive link. For data transmission, the proposed system employs frequency-shift keying (FSK) based on frequency-splitting enhancement (FSE), which is enabled by dynamic link-load isolation (LLI) and time-interleaved $LC$ resonance. This approach effectively addresses the conventional tradeoffs among power delivered to the load (PDL), data rate (DR), and power transfer efficiency (PTE). The dynamic LLI decouples the load during each resonance phase, which is critical for enabling FSE, and is implemented using a quasi-resonant boost converter (QRBC) that provides a boosted and regulated output voltage. For time-interleaved operation, reliable peak detection is achieved by a body-tuned peak detector (BTPD), which maintains accurate timing across varying link conditions. A frequency-to-amplitude converter enhances sensitivity by amplifying envelope differences, enabling robust data demodulation even in the miniaturized link. The presented ICs, fabricated in a 180-nm bipolar-CMOS-DMOS (BCD) process, simultaneously achieve 60.2% overall PTE, 43.4-mW PDL, and 1-Mb/s DR with a sub-centimeter receiver (RX) coil. As a result, the figure of merit (FoM) for data transmission is improved to a level comparable to previous works using centimeter-scale links, while the FoM for power delivery is improved by $2.5\times $ compared to prior state-of-the-art systems, employing a single inductive link.

Intelligent digital apparel, which integrates electronic functionalities into clothing, represents the future of healthcare and ubiquitous control in wearable devices. Realizing such apparel necessitates developing meter-scale conductive fibers with high toughness, conductivity, stable conductance under deformation, and mechanical durability. In this study, we present a heterostructure printing method capable of producing meter-scale (~50 m) biphasic conductive fibers that meet these criteria. Our approach involves encapsulating deformable liquid metal particles (LMPs) within a functionalized thermoplastic polyurethane matrix. This encapsulation induces in situ assembly of LMPs during fiber formation, creating a heterostructure that seamlessly integrates the matrix’s durability with the LMPs’ superior electrical performance. Unlike rigid conductive materials, deformable LMPs offer stretchability and toughness with a low gauge factor. Through precise twisting using an engineered annealing machine, multiple fiber strands are transformed into robust, electrically stable meter-scale electrodes. This advancement enhances their practicality in various intelligent digital apparel applications, such as stretchable displays, wearable healthcare systems, and digital controls.

Intracellular electrophysiology, a vital and versatile technique in cellular neuroscience, is typically conducted using the patch-clamp method. Despite its effectiveness, this method poses challenges due to its complexity and low throughput. The pursuit of multi-channel parallel neural intracellular recording has been a long-standing goal, yet achieving reliable and consistent scaling has been elusive because of several technological barriers. In this work, we introduce a micropower integrated circuit, optimized for scalable, high-throughput in vitro intrinsically intracellular electrophysiology. This system is capable of simultaneous recording and stimulation, implementing all essential functions such as signal amplification, acquisition, and control, with a direct interface to electrodes integrated on the chip. The electrophysiology system-on-chip (eSoC), fabricated in 180nm CMOS, measures 2.236 mm × 2.236 mm. It contains four 8 × 8 arrays of nanowire electrodes, each with a 50 μm pitch, placed over the top-metal layer on the chip surface, totaling 256 channels. Each channel has a power consumption of 0.47 μW, suitable for current stimulation and voltage recording, and covers 80 dB adjustable range at a sampling rate of 25 kHz. Experimental recordings with the eSoC from cultured neurons in vitro validate its functionality in accurately resolving chemically induced multi-unit intracellular electrical activity.

This article presents a wireless power transfer (WPT) system that incorporates a seamless uplink data telemetry and a simultaneous shared inductor dual-output (SIDO) regulating rectification (RR) under distance variation over a single WPT link. The proposed double charging keying (DCK) uplink data modulation method assisted by a dynamic zoom control breaks the trade-off between power delivery to the load (PDL) and uplink data such that the high data-rate uplink data telemetry no longer limits the amount of PDLs. Furthermore, DCK alleviates the design difficulty in simultaneous uplink data telemetry and RR. The dynamic ZOOM-based digital control algorithm is employed to ensure reliable uplink data telemetry and rapid transient response of SIDO-RR with two $\Delta \Sigma $ -loops under distance variations. This work achieves 1.695-Mb/s uplink data rate while delivering up to 108 mW to two independent loads over 10–42-mm single-link distance. The chip fabricated in standard 65-nm CMOS occupies 0.2-mm2 active area and its performance is validated through in vivo experiments.

Light shelves provide a function to control direct sunlight and introduce daylight into indoor spaces. Also, chilled water flowing in the light shelf can mitigate local cooling demands in perimeter zones. Therefore, in this study, a thermally activated light shelf (TALS) system was proposed, and the TALS’s radiative cooling capacity was evaluated. To do this, a mock-up chamber was developed using prototypes of TALS systems based on panel configurations. It is included: ‘Insulated’ (INS), ‘Air layer’ (ARL), and ‘Air layer with fans’ (ARF), which were designed to increase thermal insulation, natural convection, and forced convection in the TALS panels, respectively. The experiment showed that the ARL and ARF increased cooling capacity by 29% and 57% compared to the INS. Natural convective heat transfer and fan-forced airflow in the TALS's air cavity contributed to improving cooling capacity. With the INS and ARL, the air temperature was recorded at 28.6°C, which requires additional space cooling. The ARF reduced air temperature up to 2.0°C because the TALS cavity fans expedited convective heat transfer and mixing air between the cavity and test chamber. The results of this study could be used to estimate TALS cooling capacity and propose an optimal design in buildings.