Srinivasulu Gundala

Task scheduling intends to map the user-submitted tasks to the available virtual machines (VMs) based on their capacity. However, the prevailing techniques fail to perform the run-time mapping between the forthcoming workload and cloud resources. This research develops the Lapin Hunt algorithm-optimized multi-parameter-enabled task scheduler (LH-MTS) to perform energy-efficient task scheduling. The task scheduling is managed using the multi-parameter task allocation controller, where the LH-MTS algorithm schedules the tasks based on the VM parameters. The scheduler uses the multi-objective parameters in the cloud to establish the maximum throughput, resource utilization, and reliability, while reducing the makespan and delay. The results reveal that the proposed LH-MTS approach attained a high throughput of 99.98 bps, showing an improvement of 7.55% and 8.25% over the existing task scheduling with multi-objective grey wolf optimizer (TSMGWO) and fruitfly hybridized cuckoo search (FHCS) algorithms. In addition, the proposed LH-MTS approach attained the makespan of 586 s, displaying a significant reduction of 46.44 s compared to TSMGWO, and 155.91 s compared to the FHCS algorithm.

This paper introduces a new low-profile linear antenna design enhanced by an Artificial Magnetic Conductor (AMC) metamaterial structure, aimed at increasing UWB antennas' performance (UWB) antennas for wireless communication networks. Utilizing monopole antenna configuration effectively, the UWB capabilities of the proposed Crescent-Shaped Circular Patch Antenna (CSCPA) are showcased. The presented antenna configuration adopts a modified circular printed radiator, boasts dimensions of 30×20×1.6 mm3 and is equipped with an integrated AMC unit. This unit comprises a circular platform surrounded by four cross-shaped slots, Exhibiting reflective characteristics across the 6–10.90 GHz frequency band. The CSCPA antenna backed by the AMC achieves an operational bandwidth from 3.7 GHz to 7.51 GHz (BW of 3.81 GHz), effectively covering the UWB spectrum. Incorporating the AMC results in a gain increase from 3.6 dBi to 7.3 dBi for the microstrip antenna. The complete dimensions of the proposed antenna stand at 36 x 36 x 14.8 mm3 (equivalent to 0.69 λ0 x 0.69 λ0 x 0.28 λ0 at 5.5 GHz), enabling coverage of the 5G sub-6 GHz new bands (n79, Wi-Fi-5, V2X/DSRC, Wi-Fi-6) for wireless communication systems.

In robotic arm controllers, the ability to shift signal levels is crucial for interfacing between different voltage domains in a processor. The level shifter (LS) has been used to convert signals operating near threshold voltage to signals operating well above the threshold voltage. Researchers have developed current mirror-based LSs to employ current mirrors, which duplicate the current from one transistor and accurately replicate it in another, ensuring precise current matching. In this research, a dynamic inverter-based level shifter (DIBLS) with an error correction circuit is implemented. One of the main issues addressed by DIBLS is the problem of current disagreement. Current disagreement arises when multiple circuit components attempt to draw current from a common source, which leads to operational problems. Furthermore, DIBLS includes a feedback inverter controlled by the output node; this feedback inverter likely plays a pivotal role in controlling and stabilizing the output voltage of operation of the LS. The results demonstrate that DIBLS offers notable advantages on increased operational speed. This speed improvement has been achieved by circumventing the threshold voltage drop associated with the feedback of the inverter and by ensuring complete output swing, addressing stability issues. Voltage shifting between 0.3 V and 1.2 V at 1 MHz having power consumption is 16.57 nW, delay 0.22 ns, and energy per transition 32.25 fJ. The entire process is executed in 45 nm in CMOS technology.

Energy Efficiency is a critical factor while designing integrated circuits. Therefore, a 1-bit full subtractor (FS) cell is proposed for lower power application by employing Gate Level Body Biasing (GLBB) scheme for Near Threshold Computing (NTC) application to conquer a unique module for achieving full swing borrow output.We evaluate power, delay, energy and the product of energy with delay (EDP) metrics with respect to C-CMOS full subtractor. The proposed feedback based with FS with GLBB technique has a total die area of 60.02 μm², while the average power, delay, and energy are 1138 pW, 242 ns, and 27.53 aJ, respectively. The results revealed that our proposed subthreshold hybrid FS circuit with GLBB scheme successfully achieved more than 10.46% average power consumption, 26.58% energy consumption reductions, and 17.98% EDP savings compared to conventional CMOS configuration and other hybrid counterparts. GLBB circuits with FS achieve performance levels that are not affordable in C-CMOS, DTMOS,and GLBB with full adder configurations. Therefore, the FS circuit serves as an efficient divider circuit in terms of detecting objects for image processing applications.

A crucial component of digital integrated circuits with numerous power domains is the level shifter (LS). The traditional topologies are currently the mirror LS and cross-coupled LS. For full-swing level conversions from extremely low voltage to the nominal voltage of the supply, ahybrid LS is proposed in this paper, which is a combination of the current mirror LS and cross-coupled LS with a swing-aware output inverter. The proposed LS circuit is designed to ensure full swing, static current-free, and limited current-contention level conversions by preserving the benefits of the current mirror and cross-coupled LS, and using them to eliminate each other’s shortcomings. The proposed hybrid LS is designed and implemented by using 45-nm technology in Cadence Virtuoso tool. Pass transistors and current limiters with multiple thresholds are included for the suggested LS. The proposed LS provides voltage conversion from 0.10 V to 1.20 V. At alevel-shifting voltage of 0.20 V, the proposed hybrid LS at 1 MHz input frequency demonstrates a delay of 8.38 ns, an average power consumption of 3.81 µW, and an energy per transition of 26.64 fJ. Additionally, the suggested LS has low delay, good supply voltage scaling, and delay scalability.

In this paper, an irregular octagonal two-port MIMO patch antenna is designed specifically for New Radio (NR) 5G applications in the mid-band sub-6 GHz. The proposed antenna comprises an irregularly shaped patch antenna equipped with a regular 50-ohm feed line and a parasitic strip line antenna, and is partially grounded. Jeans material serves as a substrate with an effective dielectric constant of 1.6 and a thickness of 1 mm. This material is studied experimentally. The proposed antenna design undergoes analysis and optimization using the ANSYS HFSS tool. Furthermore, the design incorporates the influence of the slot on both the ground plane and the parasitic strip line to optimize performance, enhance isolation, and improve impedance matching among antenna elements. The dimensions of the jeans substrate are 40 mm × 50 mm. The simulated impedance bandwidth ranged from 3.6 GHz to 7 GHz and the measured bandwidth was slightly narrower, from 4.35 GHz to 7 GHz. The simulation results demonstrated an isolation level greater than 12 dB between antenna elements, while the measured results reached 28.5 dB, and the peak gain for this proposed antenna stood at 6.74 dB. These qualities made this proposed antenna suitable for various New Radio mid-band 5G wireless applications within the sub-6 GHz band, such as N79, Wi-Fi-5/6, V2X, and DSRC applications.

A level shifter (LS) appears to be highly efficient and effective in solving voltage contentions between deep sub-threshold and core voltage levels. An input voltage-level driven split-input inverter that can create common unconnected PMOS and NMOS transistors for the input inverter is proposed, which is powered and used at the input stage to achieve maximum conversion efficiency. Layout and simulation results across different corners have demonstrated that the proposed LS is highly useful for cutting-edge nanoscale applications. It can up-convert voltage from 0.2 V to 1.2 V and down-convert from 1.2 V to 0.2 V @ 1 MHz input pulse, with a level-up or level-down mean switching delay of 1.3 ns, and a power of 9.5 nW. Moreover, the LS occupies an area of 8 μm², which is a reasonably compact size compared to the typical LS designs. Overall, the proposed voltage LS design is an efficient and effective solution that could have an ample range of applications in IoT and biomedical, wireless sensor networks.