Virupakshi Madhurima

Task scheduling intends to map the user-submitted tasks to the available virtual machines (VMs) based on their capacity. However, the prevailing techniques fail to perform the run-time mapping between the forthcoming workload and cloud resources. This research develops the Lapin Hunt algorithm-optimized multi-parameter-enabled task scheduler (LH-MTS) to perform energy-efficient task scheduling. The task scheduling is managed using the multi-parameter task allocation controller, where the LH-MTS algorithm schedules the tasks based on the VM parameters. The scheduler uses the multi-objective parameters in the cloud to establish the maximum throughput, resource utilization, and reliability, while reducing the makespan and delay. The results reveal that the proposed LH-MTS approach attained a high throughput of 99.98 bps, showing an improvement of 7.55% and 8.25% over the existing task scheduling with multi-objective grey wolf optimizer (TSMGWO) and fruitfly hybridized cuckoo search (FHCS) algorithms. In addition, the proposed LH-MTS approach attained the makespan of 586 s, displaying a significant reduction of 46.44 s compared to TSMGWO, and 155.91 s compared to the FHCS algorithm.

Multi-Factor Authentication (MFA) is a secure electronic verification method that allows users to access an application or website only after completing multiple layers of authentication. While protecting sensitive data and systems from cyber threats is critical, traditional text-based authentication methods fail to provide sufficient security. Current systems enhance security by incorporating additional layers, such as OTPs sent to mobile phones or emails, or biometric verification using facial recognition. However, these systems often rely on costly hardware, limiting their accessibility. This paper proposes an integrated Authentication System designed to achieve high levels of security using low-cost equipment. The proposed system eliminates the need for expensive hardware by utilizing images as passwords in a novel three-step authentication process. The system effectively counters various cyber threats, including malware attacks, phishing, and SQL injection, offering a cost-effective and robust solution for secure authentication.

Cybersecurity is an essential aspect of modern life, and it encompasses a wide range of topics and concepts that are critical to understanding and combating cyber threats. One of the fundamental aspects of cybersecurityis understanding the basic principles of how computers and networks work, as well as the different types of vulnerabilities and attacks that can be used by hackers to gain unauthorized access. Hackers are individuals or groups who use their knowledge and skills to gain unauthorized access to computer systems and networks. There are various types of hackers, including black hat, white hat, and gray hat hackers, each with their own motivations and techniques. Malware, which is short for malicious software, is a type of software that is designed to harm or exploit computer systems and networks. There are various types of malware, including viruses, worms, trojans, and ransomware, each with their own methods of infecting and damaging systems.

Cyber hygiene is a crucial aspect of cyber security that involves taking necessary measures to protect your digital assets from cyber threats. It involves understanding the various risks, threats, vulnerabilities, and sources of cyber attacks. Cyber threats can arise from different sources, including human error, software vulnerabilities, weak network configurations, and cybercriminals. Examples of cyber threats include phishing attacks, malware, social engineering attacks[1], and ransom ware. These threats can cause significant harm, ranging from financial loss to reputational damage, and identity theft. A digital footprint is all the information that an individual leaves behind online, which can be used to target them for cyber-attacks. Risks associated with digital footprints include cyber stalking, harassment, and identity theft. Establishing good cyber hygiene involves following best practices such as using security software, changing passwords regularly, securing your Wi-Fi network, using privacy settings, and being alert to cyber threats.

Cybersecurity for the Internet of Things (IoT) is a complicated issue in today's networked society. IoT ecosystem security is critical because of the wide range of devices, from industrial sensors to smart thermostats, each with specific vulnerabilities and features. Due to their frequently constrained processing capabilities, these devices are vulnerable to a range of cyberattacks, such as malware insertion, denial of service (DoS), and man-in-the-middle (MitM) assaults. Furthermore, the vast amount of private information that IoT devices ranging from behavioral patterns to personal information underlines how important it is to have effective data privacy safeguards. Ensuring the integrity of the IoT supply chain is another crucial aspect of cybersecurity, as tampering during manufacturing or distribution could compromise the security of devices. Regulatory compliance, such as adherence to standards like GDPR and HIPAA, adds another layer of complexity for manufacturers and service providers.

Energy Efficiency is a critical factor while designing integrated circuits. Therefore, a 1-bit full subtractor (FS) cell is proposed for lower power application by employing Gate Level Body Biasing (GLBB) scheme for Near Threshold Computing (NTC) application to conquer a unique module for achieving full swing borrow output.We evaluate power, delay, energy and the product of energy with delay (EDP) metrics with respect to C-CMOS full subtractor. The proposed feedback based with FS with GLBB technique has a total die area of 60.02 μm², while the average power, delay, and energy are 1138 pW, 242 ns, and 27.53 aJ, respectively. The results revealed that our proposed subthreshold hybrid FS circuit with GLBB scheme successfully achieved more than 10.46% average power consumption, 26.58% energy consumption reductions, and 17.98% EDP savings compared to conventional CMOS configuration and other hybrid counterparts. GLBB circuits with FS achieve performance levels that are not affordable in C-CMOS, DTMOS,and GLBB with full adder configurations. Therefore, the FS circuit serves as an efficient divider circuit in terms of detecting objects for image processing applications.

This study explores integrating renewable energy sources into microgrid systems to improve voltage quality and reduce harmonic distortion losses using an Adaptive Neuro-Fuzzy Inference System (ANFIS) controller. Microgrids with renewables offer enhanced energy reliability and efficiency but face challenges like voltage fluctuations and harmonic distortions. Renewable sources like solar and wind introduce variability, impacting voltage stability and causing harmonic distortions in the grid. The ANFIS controller adapts to these dynamics by dynamically adjusting parameters, leveraging neural network adaptability and fuzzy logic's interpretability to manage nonlinear and uncertain behaviors typical of renewables. The research aims to optimize microgrid performance by mitigating voltage fluctuations and harmonic distortions through ANFIS. By improving operational stability and efficiency, this approach supports effective renewable energy integration into broader grid infrastructures. Through empirical analysis and simulations, the study provides insights into ANFIS's practical application in microgrid management, contributing to sustainable energy solutions and grid resilience.This research underscores the importance of ANFIS controllers in enhancing renewable energy integration within microgrid systems, offering actionable strategies for improving energy sustainability and reliability in modern power networks.

A crucial component of digital integrated circuits with numerous power domains is the level shifter (LS). The traditional topologies are currently the mirror LS and cross-coupled LS. For full-swing level conversions from extremely low voltage to the nominal voltage of the supply, ahybrid LS is proposed in this paper, which is a combination of the current mirror LS and cross-coupled LS with a swing-aware output inverter. The proposed LS circuit is designed to ensure full swing, static current-free, and limited current-contention level conversions by preserving the benefits of the current mirror and cross-coupled LS, and using them to eliminate each other’s shortcomings. The proposed hybrid LS is designed and implemented by using 45-nm technology in Cadence Virtuoso tool. Pass transistors and current limiters with multiple thresholds are included for the suggested LS. The proposed LS provides voltage conversion from 0.10 V to 1.20 V. At alevel-shifting voltage of 0.20 V, the proposed hybrid LS at 1 MHz input frequency demonstrates a delay of 8.38 ns, an average power consumption of 3.81 µW, and an energy per transition of 26.64 fJ. Additionally, the suggested LS has low delay, good supply voltage scaling, and delay scalability.

A level shifter (LS) appears to be highly efficient and effective in solving voltage contentions between deep sub-threshold and core voltage levels. An input voltage-level driven split-input inverter that can create common unconnected PMOS and NMOS transistors for the input inverter is proposed, which is powered and used at the input stage to achieve maximum conversion efficiency. Layout and simulation results across different corners have demonstrated that the proposed LS is highly useful for cutting-edge nanoscale applications. It can up-convert voltage from 0.2 V to 1.2 V and down-convert from 1.2 V to 0.2 V @ 1 MHz input pulse, with a level-up or level-down mean switching delay of 1.3 ns, and a power of 9.5 nW. Moreover, the LS occupies an area of 8 μm², which is a reasonably compact size compared to the typical LS designs. Overall, the proposed voltage LS design is an efficient and effective solution that could have an ample range of applications in IoT and biomedical, wireless sensor networks.