Wan-Soo Park
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Wan-Soo Park has a total of 24 co-authors. Here are the top co-authors by number of shared publications:
- Dae-Hyun Kim
Kyungpook National University
5 shared publications - Hiroki Sugiyama
NTT Device Technology Laboratories, Atsugi-shi 243-0198, Japan
4 shared publications - Hyeon-Bhin Jo
Department of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South Korea
4 shared publications - In-Geun Lee
Department of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South Korea
4 shared publications Jae-Hak Lee
Department of Electronic and Electrical Engineering, Kyungpook National University, Daegu, South Korea
4 shared publications- Tae-Woo Kim
Department of Electrical, Electronic and Computer Engineering, University of Ulsan, Ulsan 44610, Republic of Korea
4 shared publications
Latest Publications
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 73 (8) , 1-6
Investigation of Gate Field-Plate Effects on f max Improvement in GaN HEMTs for RF Applications
- 1 January 2026
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 73 (8) , 1-6
Investigation of Gate Field-Plate Effects on f max Improvement in GaN HEMTs for RF Applications
- 10 January 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 70 (4) , 2081-2089
Sub-50 nm Terahertz In0.8Ga0.2As Quantum-Well High-Electron-Mobility Transistors for 6G Applications
We present a systematic study on the gate length (${L}_{{g}}\text {)}$ scaling behavior and the impact of the side-recess spacing (${L}_{\text {side}}\text {)}$ on dc and high-frequency characteristics of In0.8Ga0.2As quantum-well (QW) high-electron-mobility transistors (HEMTs) with${L}_{{g}}$ from 10$\mu $ m to 20 nm, for the purpose of understanding the scaling limit of maximum oscillation frequency (${f}_{\text {max}}\text {)}$ and thereby demonstrating terahertz devices. The fabricated In0.8Ga0.2As QW HEMTs with${L}_{{g}} =20$ nm and${L}_{\text {side}} =150$ nm exhibited values of drain-induced-barrier-lowering (DIBL) of 60 mV/V, current-gain cutoff frequency (${f}_{{T}}\text {)}$ of 0.75 THz, and${f}_{\text {max}}$ of 1.1 THz, while the device with${L}_{\text {side}} =50$ nm showed DIBL of 110 mV/V and${f}_{{T}}$ /${f}_{\text {max}}$ of 0.72/0.53 THz. It was central to strictly control short-channel effects (SCEs) from the perspective of DIBL to maximize the improvement of${f}_{\text {max}}$ , as${L}_{{g}}$ was scaled down deeply. In an effort to understand the${L}_{{g}}$ scaling behavior of${f}_{\text {max}}$ , we carried out the small-signal modeling for both types of devices and found that the increase of the intrinsic output conductance (${g}_{\text {oi}}\text {)}$ played a critical role in determining${f}_{\text {max}}$ in short-${L}_{{g}}$ HEMTs. On the contrary, the fabricated devices with${L}_{\text {side}} =150$ nm exhibited a tight control of SCEs at${L}_{{g}}$ of 20 nm. As a result,${f}_{\text {max}}$ in those devices was boosted to 1.1 THz, and more importantly this high${f}_{\text {max}}$ was maintained even as${L}_{{g}}$ was scaled down to 20 nm. The results in this work represent the best balance of${f}_{{T}}$ and${f}_{\text {max}}$ in any transistor technology on any material system, displaying both${f}_{{T}}$ and${f}_{\text {max}}$ in excess of 700 GHz simultaneously.- 10 January 2023
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Electron Devices
- Vol. 70 (4) , 2081-2089
Sub-50 nm Terahertz In0.8Ga0.2As Quantum-Well High-Electron-Mobility Transistors for 6G Applications
We present a systematic study on the gate length (${L}_{{g}}\text {)}$ scaling behavior and the impact of the side-recess spacing (${L}_{\text {side}}\text {)}$ on dc and high-frequency characteristics of In0.8Ga0.2As quantum-well (QW) high-electron-mobility transistors (HEMTs) with${L}_{{g}}$ from 10$\mu $ m to 20 nm, for the purpose of understanding the scaling limit of maximum oscillation frequency (${f}_{\text {max}}\text {)}$ and thereby demonstrating terahertz devices. The fabricated In0.8Ga0.2As QW HEMTs with${L}_{{g}} =20$ nm and${L}_{\text {side}} =150$ nm exhibited values of drain-induced-barrier-lowering (DIBL) of 60 mV/V, current-gain cutoff frequency (${f}_{{T}}\text {)}$ of 0.75 THz, and${f}_{\text {max}}$ of 1.1 THz, while the device with${L}_{\text {side}} =50$ nm showed DIBL of 110 mV/V and${f}_{{T}}$ /${f}_{\text {max}}$ of 0.72/0.53 THz. It was central to strictly control short-channel effects (SCEs) from the perspective of DIBL to maximize the improvement of${f}_{\text {max}}$ , as${L}_{{g}}$ was scaled down deeply. In an effort to understand the${L}_{{g}}$ scaling behavior of${f}_{\text {max}}$ , we carried out the small-signal modeling for both types of devices and found that the increase of the intrinsic output conductance (${g}_{\text {oi}}\text {)}$ played a critical role in determining${f}_{\text {max}}$ in short-${L}_{{g}}$ HEMTs. On the contrary, the fabricated devices with${L}_{\text {side}} =150$ nm exhibited a tight control of SCEs at${L}_{{g}}$ of 20 nm. As a result,${f}_{\text {max}}$ in those devices was boosted to 1.1 THz, and more importantly this high${f}_{\text {max}}$ was maintained even as${L}_{{g}}$ was scaled down to 20 nm. The results in this work represent the best balance of${f}_{{T}}$ and${f}_{\text {max}}$ in any transistor technology on any material system, displaying both${f}_{{T}}$ and${f}_{\text {max}}$ in excess of 700 GHz simultaneously.- 21 December 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 44 (2) , 229-232
A New Methodology to Analyze Carrier Transport Properties for In x Ga1−x As Quantum-Well High-Electron Mobility Transistors From Transconductance in Saturation
Conventional techniques to characterize the carrier transport properties in high-electron-mobility transistors do not account for the effect of each individual unit process and device integration, and can be challenging to use for short-channel devices. To overcome this, we have developed a new technique that consists of measurement and analysis of the transconductance scaling behavior. The proposed ${g}_{m}$ modeling technique yielded the effective mobility, $\mu _{n\_{}{\textit {eff}}}$ , and saturation velocity, ${v}_{\textit {sat}}$ for fabricated InxGa $_{{1}-{x}}$ As Quantum-Well (QW) HEMTs, correlating the carrier transport properties to the device characteristics. This helps illuminate the physics of the carrier transport properties of HEMTs from the mobility relevant to the velocity saturation regimes.
- 21 December 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 44 (2) , 229-232
A New Methodology to Analyze Carrier Transport Properties for In x Ga1−x As Quantum-Well High-Electron Mobility Transistors From Transconductance in Saturation
Conventional techniques to characterize the carrier transport properties in high-electron-mobility transistors do not account for the effect of each individual unit process and device integration, and can be challenging to use for short-channel devices. To overcome this, we have developed a new technique that consists of measurement and analysis of the transconductance scaling behavior. The proposed ${g}_{m}$ modeling technique yielded the effective mobility, $\mu _{n\_{}{\textit {eff}}}$ , and saturation velocity, ${v}_{\textit {sat}}$ for fabricated InxGa $_{{1}-{x}}$ As Quantum-Well (QW) HEMTs, correlating the carrier transport properties to the device characteristics. This helps illuminate the physics of the carrier transport properties of HEMTs from the mobility relevant to the velocity saturation regimes.
- Open Access
- 6 May 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of the Electron Devices Society
- Vol. 10, 387-396
Physics-Based Analytical Channel Charge Model of In x Ga1-x As/In0.52Al0.48As Quantum-Well Field-Effect Transistors From Subthreshold to Strong Inversion Regimes
This paper presents a physics-based analytical channel charge model for indium-rich In x Ga 1-x As/In 0.52 Al 0.48 As quantum-well (QW) field-effect transistors (FETs) that is applicable from the subthreshold to strong inversion regimes. The model requires only seven physical/geometrical parameters, along with three transition coefficients. In the subthreshold regime, the conduction bands ($E_{C}$ ) of all regions are flat with finite and symmetrical QW configurations. Since the Fermi–level ($E_{F}$ ) is located far below$E_{C}$ , the two-dimensional electron-gas density ($n_{2{-}DEG}$ ) should be minimal and can thus be approximated from Maxwell–Boltzmann statistics. In contrast, the applied gate bias lowers the$E_{C}$ of all structures in the inversion regime, yielding band-bending of an In 0.52 Al 0.48 As insulator and In x Ga 1-x As QW channel. The dependency of the energy separation between$E_{F}$ and$E_{C}$ on the surface of the In x Ga 1-x As QW channel upon$V_{GS}$ enables construction of the charge–voltage behaviors of In x Ga 1-x As/In 0.52 Al 0.48 As QW FETs. To develop a unified, continuous and differentiable areal channel charge density ($Q_{ch}$ ) model that is valid from the subthreshold to strong inversion regimes, the previously proposed inversion-layer transition function is further revised with three transition coefficients of$\eta $ ,$\alpha $ and$\beta $ in this work. To verify the proposed approach, the results of the proposed model are compared with those of not only the numerically calculated Qch from a one-dimensional (1D) Poisson–Schrödinger solver, but also the measured gate capacitance of a fabricated In 0.7 Ga 0.3 As QW metal-insulator-semiconductor FET with large gate length, yielding excellent agreement between the simulated and measured results.- 6 May 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Journal of the Electron Devices Society
- Vol. 10, 387-396
Open AccessPhysics-Based Analytical Channel Charge Model of In x Ga1-x As/In0.52Al0.48As Quantum-Well Field-Effect Transistors From Subthreshold to Strong Inversion Regimes
This paper presents a physics-based analytical channel charge model for indium-rich In x Ga 1-x As/In 0.52 Al 0.48 As quantum-well (QW) field-effect transistors (FETs) that is applicable from the subthreshold to strong inversion regimes. The model requires only seven physical/geometrical parameters, along with three transition coefficients. In the subthreshold regime, the conduction bands ($E_{C}$ ) of all regions are flat with finite and symmetrical QW configurations. Since the Fermi–level ($E_{F}$ ) is located far below$E_{C}$ , the two-dimensional electron-gas density ($n_{2{-}DEG}$ ) should be minimal and can thus be approximated from Maxwell–Boltzmann statistics. In contrast, the applied gate bias lowers the$E_{C}$ of all structures in the inversion regime, yielding band-bending of an In 0.52 Al 0.48 As insulator and In x Ga 1-x As QW channel. The dependency of the energy separation between$E_{F}$ and$E_{C}$ on the surface of the In x Ga 1-x As QW channel upon$V_{GS}$ enables construction of the charge–voltage behaviors of In x Ga 1-x As/In 0.52 Al 0.48 As QW FETs. To develop a unified, continuous and differentiable areal channel charge density ($Q_{ch}$ ) model that is valid from the subthreshold to strong inversion regimes, the previously proposed inversion-layer transition function is further revised with three transition coefficients of$\eta $ ,$\alpha $ and$\beta $ in this work. To verify the proposed approach, the results of the proposed model are compared with those of not only the numerically calculated Qch from a one-dimensional (1D) Poisson–Schrödinger solver, but also the measured gate capacitance of a fabricated In 0.7 Ga 0.3 As QW metal-insulator-semiconductor FET with large gate length, yielding excellent agreement between the simulated and measured results. - 13 April 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 42 (6) , 804-807
A Comprehensive Benchmarking Method for the Net Combination of Mobility Enhancement and Density-of-States Bottleneck
In this paper, we propose a comprehensive benchmarking method to simultaneously address mobility enhancement and density-of-states bottleneck in advanced field-effect-transistors (FETs) with novel high-mobility (high-μ) channel materials, where we focused on conventional covalent bonding semiconductors with pure and partially ionic character. This method relies only on the measured extrinsic transconductance of a long-channel FET in the saturation regime together with the source resistance, yielding the product of the effective mobility (μeff) and effective gate capacitance (Cgeff). We tested this method in InxGa1-xAs quantum-well high-electron-mobility transistors (HEMTs) with various indium mole fractions, such as 0.53, 0.7, 0.8 and 1, as well as in Si n-FETs. We found that the InxGa1-xAs HEMTs with μeff over 10,000 cm2/V∙s at 300 K provided more than 20 times greater μeff × Cgeff than Si n-FETs. More specifically, the product initially improved as x increased, then showed a peak value of 10,300 μF∙V-1∙s-1 at x of around 0.8, and degraded slightly beyond that composition. To verify the validness of the proposed method, we separately measured and analyzed Cgeff and μeff using the split-CV technique, showing excellent agreement with the ones from the proposed method.
- 13 April 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Electron Device Letters
- Vol. 42 (6) , 804-807
A Comprehensive Benchmarking Method for the Net Combination of Mobility Enhancement and Density-of-States Bottleneck
In this paper, we propose a comprehensive benchmarking method to simultaneously address mobility enhancement and density-of-states bottleneck in advanced field-effect-transistors (FETs) with novel high-mobility (high-μ) channel materials, where we focused on conventional covalent bonding semiconductors with pure and partially ionic character. This method relies only on the measured extrinsic transconductance of a long-channel FET in the saturation regime together with the source resistance, yielding the product of the effective mobility (μeff) and effective gate capacitance (Cgeff). We tested this method in InxGa1-xAs quantum-well high-electron-mobility transistors (HEMTs) with various indium mole fractions, such as 0.53, 0.7, 0.8 and 1, as well as in Si n-FETs. We found that the InxGa1-xAs HEMTs with μeff over 10,000 cm2/V∙s at 300 K provided more than 20 times greater μeff × Cgeff than Si n-FETs. More specifically, the product initially improved as x increased, then showed a peak value of 10,300 μF∙V-1∙s-1 at x of around 0.8, and degraded slightly beyond that composition. To verify the validness of the proposed method, we separately measured and analyzed Cgeff and μeff using the split-CV technique, showing excellent agreement with the ones from the proposed method.