Ignacio M. Delgado-Lozano

In this paper the authors describe the design of a broadband aperture-stacked patch (ASP) microstrip antenna based on a filtering equivalent circuit. The antenna consists of two stacked microstrip patches that are fed by a microstrip line through a resonant aperture. An equivalent circuit is proposed for the antenna consisting of three LC parallel resonators, out of which two resonators are inductively coupled and two resonators are capacitively coupled. The equivalent circuit is de-embedded from the antenna response by means of the least squares method, and the dimensions of the antenna are adjusted in such a way their equivalent circuit matches the response of a broadband third order filter. The reference filter is used as a mean to ensure broadband matching of the antenna. Following this design strategy, a broadband ASP antenna has been designed, fabricated and measured at a center frequency of 5.5 GHz with a bandwidth of roughly 45%.

This paper proposes the design of broadband microstrip antennas fed by differential microstrip lines. The designed broadband antennas are composed of two capacitively coupled rectangular stacked patches excited through a dog-bone shaped aperture by short-circuited differential microstrip lines. The short-circuited lines are symmetrically located with respect to the apertures so that their differential-mode (DM) naturally excites the aperture, while their common-mode (CM) is intrinsically rejected. The DM design of the antennas is based on an equivalent second-order filter circuit consisting of two capacitively coupled parallel LC resonators, which helps to ensure the DM broadband impedance matching of the antenna. Two different 2 × 2 arrays using the proposed antennas have been designed, fabricated and measured, one involving four 180° hybrids and three power dividers in the feeding network, the other involving one 180° hybrid and six power dividers. Bandwidths larger than 25%, gains around 12 dBi and cross-polarization below -25 dB have been achieved by the two arrays at a center frequency of 5.5 GHz.

Attestation is a strong tool to verify the integrity of an untrusted system. However, in recent years, different attacks have appeared that are able to mislead the attestation process with treacherous practices as memory copy, proxy, and rootkit attacks, just to name a few. A successful attack leads to systems that are considered trusted by a verifier system, while the prover has bypassed the challenge. To mitigate these attacks against attestation methods and protocols, some proposals have considered the use of side-channel information that can be measured externally, as it is the case of electromagnetic (EM) emanation. Nonetheless, these methods require the physical proximity of an external setup to capture the EM radiation. In this paper, we present the possibility of performing attestation by using the side-channel information captured by a sensor or peripheral that lives in the same System-on-Chip (SoC) than the processor system (PS) which executes the operation that we aim to attest, by only sharing the Power Distribution Network (PDN). In our case, an analog-to-digital converter (ADC) that captures the voltage fluctuations at its input terminal while a certain operation is taking place is suitable to characterize itself and to distinguish it from other binaries. The resultant power traces are enough to clearly identify a given operation without the requirement of physical proximity.

The design of near future cryptocircuits will require greater performance characteristics in order to be implemented in devices with very limited resources for secure applications. Considering the security against differential power side-channel attacks (DPA), explorations of different implementations of dual-precharge logic gates with advanced and emerging technologies, using nanometric FinFET and Tunnel FET transistors, are proposed aiming to maintain or even improve the security levels obtained by current Metal-Oxide Semiconductor Field-Effect Transistor (MOSFET) technologies and reducing the resources needed for the implementations. As case study, dual-precharge logic primitives have been designed and included in the 4-bit substitution box of PRIDE algorithm, measuring the performance and evaluating the security through simulation-based Differential Power Analysis (DPA) attacks for each implementation. Extensive electrical simulations with predictive Predictive Transistor model on scaled 16nm and 22nm MOSFET, 16nm and 20nm FinFET, and 20nm Tunnel Field Effect Transistor (TFET) demonstrate a clear evolution of security and performances with respect to current 90nm MOSFET implementations, providing FinFET as fastest solutions with a delay 3.7 times better than conventional proposals, but TFET being the best candidate for future cryptocircuits in terms of average power consumption (x0.02 times compared with conventional technologies) and security in some orders of magnitude.