Srikant Kumar Mohanty

In this study, AlZnON thin-film transistors (TFTs) were fabricated by incorporating aluminum into the ZnON semiconductor and further Schottky contact on the surface of the channel is implemented to enhance the electrical and optical performance of the device. The presence of Al in the thin film improves the reliability of the TFT by stabilizing the nitrogen bond. Further, the optical transmittance improved to 90% from 80% and the bandgap increased to 2.48 eV from 1.89 eV with the doping of Al. The effects of the work function and the widths of the Schottky metal contact on the device characteristics are also investigated. The optimum structure is realized with high work function (5.65 eV) platinum (Pt) metal contact which was positioned at the center of the channel and the width of the Schottky contact was 0.25 times the length of the channel. With the encapsulation of this optimum surface-engineered Schottky contact (SESC) in the device, the field effect mobility increased from 27.3 to 43.9 cm² V⁻¹·s⁻¹, the subthreshold swing reduced from 196 to 113 mV dec⁻¹, threshold voltage changed from −0.13 to 0.12 V and the on–off current ratio improved from 4.13 × 10⁶ to 1.03 × 10⁸. The substantial enhancement of transistor performance is achieved through the utilization of a high-work function metal layer, which generates a larger depletion region in the channel, and by precisely controlling the width of the Schottky contact at the channel’s center, the depletion region is optimized to suppress off-current while maintaining improved field effect mobility. From the above result, it is evident that the proposed SESC in Al-doped ZnON TFT is a promising candidate for next-generation display application.

In this work, we investigated the effect of the tungsten nitride (WNx) diffusion barrier layer on the resistive switching operation of the aluminum nitride (AlN) based conductive bridge random access memory. The WNx barrier layer limits the diffusion of Cu ions in the AlN switching layer, hence controlling the formation of metallic conductive filament in the host layer. The device operated at a very low operating voltage with a V_set of 0.6 V and a V_reset of 0.4 V. The spatial and temporal switching variability were reduced significantly by inserting a barrier layer. The worst-case coefficient of variations (σ/µ) for HRS and LRS are 33% and 18%, respectively, when barrier layer devices are deployed, compared to 167% and 33% when the barrier layer is not present. With a barrier layer, the device exhibits data retention behavior for more than 10⁴ s at 120 °C, whereas without a barrier layer, the device fails after 10³ s. The device demonstrated synaptic behavior with long-term potentiation/depression (LTP/LTD) for 30 epochs by stimulating with a train of identical optimized pulses of 1 µs duration.

In this study, we investigated the effect of microwave-irradiation annealing (MWA) and thermal furnace annealing (FA) in oxygen ambient on the active channel layer of p-type tin-oxide (SnO) thin-film transistors. At very low source-drain voltage of −0.1 V, the MWA at 1200 W and FA at 300 °C samples have exhibited significant improvement in the electrical characteristics such as subthreshold swing (SS) of 0.93 and 0.485 V dec ⁻¹ , the I _on / I _off ratio of 1.65 × 10 ⁴ and 3.07 × 10 ⁴ , the field-effect mobility ( μ _FE ) of 0.16 and 0.26 cm ² V ⁻¹ s and ultra-low off-state current of 1.9 and 2.0 pA respectively. The observed performance enhancement was mainly attributed to the reduction of interface trap density ( N _t ) by tuning the power of MWA and optimizing the temperature in FA. From the result, we observed the optical band gap ( E _g ) increased by 6% in FA, and 12% in MWA, which confirms improved crystallinity and reduction of defect states. Additionally, a low thermal budget microwave anneal process has shown high transmittance of more than 86% in the visible region (380–700 nm). The physical characterization indicates the partial phase transformation of SnO to SnO ₂ with retaining p-type conductivity in both annealing processes. The results demonstrate that both the annealing process could be highly promising to be used in the complementary logic circuits of new generation flexible/transparent displays.

Gradual conduction tuning with a large memory window is essential for realizing multilevel switching memristive devices. In this work, we demonstrated 3-bit per cell storage capability with excellent endurance and retention behavior of AlN/AlO memristor via interface engineering. By incorporating an ultra-thin 2 nm Al ₂ O ₃ interface layer, seven distinct high resistance states with same low resistance state were achieved by controlling reset-stop voltage. In addition, by varying set compliance current, six resistance states with reliability and reproducibility were illustrated. The maximum cycle-to-cycle variability $\sigma /\mu $ (standard deviation/mean) of any resistance state was 28.7% in reset-stop voltage control methods. The multilevel switching characteristics could be attributed to (a) enhancement of on-off ratio resulted due to insertion of Al ₂ O ₃ barrier layer acts as series resistance (b) the gradual electron detrapping from occupied trap sites resulting in multiple intermediate resistance states during reset.