Xiaojing Li

Spin–orbit torque magnetic tunnel junctions (SOT-MTJs) have attracted interest as potential candidates for radiation-tolerant memory applications because of their high speed, low power consumption, and high endurance. Although SOT-MTJs utilize spin for data storage, operations are performed by applying different electrical biases. In conventional silicon-based devices, the applied electric field typically accelerates radiation-induced defect accumulation and dielectric breakdown, and the dynamic radiation stability of SOT-MTJs under these conditions remains largely unexplored. Therefore, we investigated the total ionizing dose and single-event effects of SOT-MTJs under electrical bias using 10 keV x-ray and 1673 MeV Ta-ion irradiation, respectively. Under various bias conditions and dose rates, the tunnel magnetoresistance (TMR) and critical switching current (Ic) of the SOT-MTJs remained highly stable even at a total dose of 1.5 Mrad(Si), with TMR fluctuations of less than 2%. Devices subjected to heavy-ion irradiation exhibited no abnormal switching or breakdown in either the anti-parallel (AP) or parallel (P) state. Furthermore, the average TMR variation in the unbiased device arrays was approximately 1%, while the average Ic remained nearly unchanged. These results demonstrate the radiation stability of the fabricated 320 × 1100 nm2 in-plane SOT-MTJ test vehicles under the investigated total ionizing-dose and heavy-ion irradiation conditions, while providing a device-level reference for future radiation studies of scaled SOT-MRAM technologies.

Three-dimensional complementary metal-oxide-semiconductor technology integrating carbon nanotubes and silicon presents a promising pathway for the fabrication of beyond-Moore integrated circuits. Herein, we present an ionizing-irradiation-involved integration process towards ultra-low-power fabrication, completely compatible with the 3D integration process. As the fundamental building blocks of digital circuits, inverter cells are examined to verify the effectiveness of this proposed methodology. Furthermore, comparative experiments combined with numerical simulations are utilized to thoroughly investigate transistor-level radiation effects, revealing the governing mechanisms of power reduction. By incorporating Cobalt-60 γ-ray irradiation within the wafer-scale 180-nm-node 3D integration, the threshold voltage mismatch between p-type and n-type transistors can be resolved without significant modifications to the process flow. With optimized ionizing radiation doses and bias conditions, the switching threshold voltages of the 3D CMOS inverters improves from 0.400× to 0.495× of the supply voltage V_DD (a 24.2% improvement), closely approaching the ideal value of 0.5× V_DD. This optimization leads to a distinct increase in the noise margin low from 0.276× to 0.373× V_DD (a 35.1% enhancement), significantly boosting the reliability of the digital circuit cells. More importantly, the minimal operational V_DD of the inverters is remarkably reduced from 0.5 to 0.2 V. An ultra-low minimal peak dynamic power of 8.33 pW (831× reduction by the ionizing irradiation) is achieved, which is amongst the lowest values in publications.

This work introduces a novel post-fabrication electromagnetic pulse (EMP) injection technique for optimizing the on-resistance–breakdown voltage (R_ON-BV) trade-off in bulk lateral double-diffused MOSFETs. Experimental results demonstrate significantly higher BV modulation efficiency in devices with thick gate oxides compared to thin gate oxide counterparts with unchanged on-resistance (R_ON). This comparative analysis combined with AI-assisted TCAD simulations conclusively identifies the unique distribution of trapped charges within the gate oxide as the dominant mechanism responsible for BV shift. These findings demonstrate that the post-process EMP-induced BV enhancement without typical degradation in R_ON provides a new approach for overcoming the fundamental R_ON-BV trade-off in power semiconductors.

In this article, the electrostatic discharge (ESD) performance of gate‐structure‐defined diodes (gated diodes) based on stacked SiGe/Si fin field‐effect transistor (FinFET), Si channel gate‐all‐around field‐effect transistor (GAA), and SiGe channel GAA structure in GAA technology is investigated in detail by using 3D TCAD simulations. The stacked SiGe/Si FinFET demonstrates superior ESD robustness, exhibiting a significantly higher failure current (I _t2 ) and the lowest on‐resistance ( R _on ) among the tested structures. Meanwhile, the transmission line pulse (TLP) current conduction and failure mechanism in these gated diodes are examined through physical analysis. The results reveal that current crowding leads to early thermal failure and I _t2 deterioration. Additionally, the I _t2 of stacked SiGe/Si FinFET can be further improved by 6% as the Si and SiGe thickness ratios are optimized from 6/12 to 12/6 nm. These findings suggest that the optimized stacked SiGe/Si FinFET gated diode is a promising candidate for ESD protection in GAA technology.

Protecting integrated circuits against electrostatic discharge (ESD) remains a persistent challenge within the semiconductor industry, garnering significant attention from the research and industrial sectors. To effectively discharge substantial ESD current away from sensitive devices, on-chip ESD protection is required to become conductive within mere nanoseconds and then return to an insulated state after the event. Insulator-metal transition (IMT) materials intrinsically possess this property. Little research has been done on the electrostatic discharge characteristics of the well-known IMT material Niobium oxide (NbO2). In this study, we execute transmission line pulse (TLP) assessments on 50-nm NbOx vertical construct and analyze ESD characteristics and failure mechanisms utilizing X-ray photoelectron spectroscopy, scanning electron microscopy, etc. The snapback behavior is observed in the device’s TLP I-V curve. The results show the promise of IMT materials for on-chip ESD/EOS protection.

A novel silicon-controlled rectifier (SCR) device is proposed to achieve adjustable holding voltage (V_h) and strong radiation tolerance. The proposed SCR devices are fabricated in 0.18-μm silicon-on-insulator (SOI) technology by inserting the very shallow trench isolation (VSTI) with different lengths in the n-well between the anode region and polysilicon. The adjustable V_h ranging from 2.0 to 4.8 V is achieved by changing the length of VSTI from 0.3 to 3 μm. The influence of total ionizing dose (TID) on VSTI-SCR devices is investigated by experiments and simulations, and strong radiation tolerance up to 500 krad(Si) is proved for the VSTI-SCRs. It is concluded that its triggering voltage decreases by about 19%–31% with the radiation dose increase from 0 to 500 krad(Si), which is beneficial for the operation of VSTI-SCR devices. V_h decreases by approximately 15%, which is overlapped by the ESD-design window of 1.2× V_DD–0.8× V_BD. Whereas, as the length of VSTI increases, V_h elevates and the effect of TID on V_h of SCR devices remains almost unchanged, which means that the latch-up risk of VSTI-SCR induced by TID could be eliminated by broadening VSTI length properly.

The electrostatic discharge (ESD) and failure mechanisms of carbon nanotube field-effect transistors (CNT FETs) were thoroughly investigated via transient current tests and numerical simulations. Experiments demonstrated that CNT FETs have a three-stage ESD process according to transmission-line pulse (TLP) and human-body model (HBM) measurements, vastly different from the snapback phenomenon in conventional Si CMOS transistors. As the drain bias (V_DS) increases from 2 to 12 V, the ESD mechanism of CNT FETs changes from thermionic emission (first stage) to band-to-band tunneling (second stage), which results in a dynamic discharge impedance. The soft breakdown of the drain-to-gate isolation dielectric contributes to the discharge current in the third stage when V_DS > 12 V. The breakdown current-induced heating of CNT FETs can cause critical damage to the drain-to-gate isolation dielectric and the metal contacts and eventually result in device failure. Therefore, the drain-to-gate isolation dielectric is identified as the weak spot, requiring optimization to enhance the reliability of CNT FETs.

The total ionizing dose (TID) effect in p-type top-gate CNT FET under ON, OFF, TG, and All-0 bias conditions is investigated through experiments and simulations. The continuous application of electrical stress incites degradation in the device characteristics of CNT FETs, which is further complicated by the superimposition of TID effects. This work distinguished between the electrical stress impact and the TID effect through comparative experiments and analyzed the underlying mechanisms of these two effects with TCAD simulations. The experimental results demonstrate that both effects on CNT FETs mainly result in a threshold voltage shift. Electrical stress results in a ΔV_th of -0.1 V (OFF state) to +0.2 V (ON state), while TID effect results in a ΔV_th of -0.15 V (TG state) to -0.05 V (ON and OFF state). The TG state is recognized as the worst-case bias condition of TID effect on CNT FETs. TCAD simulation results denote that electrical stress incites changes in the trap charge density (~10¹² cm^-2) within the gate dielectric layer, while the TID effect augments positive fixed charges (~10¹¹ to 10¹² cm^-2) in the substrate oxide. This study explains the mechanisms of electrical stress and TID effects in CNT FETs, providing a reference for subsequent device process optimization and radiation hardening.

The impact of the total ionizing dose (TID) on low leakage electrostatic discharge (ESD) protection devices fabricated on the 180-nm double silicon on insulator (DSOI) technology is investigated through experiments and numerical simulations. The devices under tests (DUTs) are MOS-DIO, MOS-SCR, and gate-grounded NMOSFET (GGNMOS). The transmission line pulse (TLP) measurements were carried out before and right after $^{\text{60}}$ Co gamma ray irradiation. The results show that the radiation-induced charges and traps mainly located in the top buried oxide (BOX1) can lead to deterioration of ESD characteristics, such as leakage and triggering voltage. After being irradiated to a dose of 300 krad(Si), the leakage of GGNMOS increases by about three orders of magnitude, and in addition, its snapback characteristic vanishes. Radiation hardness on DSOI-based ESD devices is analyzed based on experiment and simulation results, which implies that the negative voltage on back-gate electrode can mitigate the deterioration of ESD characteristics caused due to irradiation.