Chuanbin Zeng

In the architecture of system-on-chip (SoC) design, the bus plays a critical role by facilitating inter-module connections and managing data transmission. Although the commercial bus solutions represented by the Cortex-M System Design Kit (CMSDK) are widely adopted in the industry, they exhibit lower communication efficiency in certain specialized requirements. This research focuses on optimizing the transition from a 32-bit high-speed intra-core bus to a 64-bit low-speed AHB-Lite bus. A new solution (MergFS) for this conversion process is proposed and implemented, which supports request merging and dynamic frequency switching. Experimental results show that, compared to the solution using CMSDK, MergFS reduces clock cycles by approximately 50% to 75% when processing multiple transactions. Additionally, synthesis results under the three different technologies show MergFS introduces ~4.5% area and ~6.02% power overhead on average.

Current processor chip designs are mainly oriented by performance, power and area (PPA), and developed using the waterfall model. However, there are two main challenges in this development model: 1) The end-to-end iteration cycle and cost of processor chip development are too high, and cannot flexibly respond to changes in chip fragmented design specifications. 2) Processor chip verification is less agile, and there is a lack of a full-chain processor agile design platform that can be easily ported to different development environments. To tackle both issues, we propose an object-oriented hardware agile design methodology, oriented by time, cost, and complexity, and have built the RIVL platform to support the agile development process for processors. RIVL integrates a highly automated design flow for processor RTL design, Integration, Verification, and Layout design to improve processor development efficiency. We achieved tape-out verification of more than 60 RISC-V processors through agile design methods, demonstrating the use and effectiveness of RIVL. We quantify the performance of CoreGen using CoreMark and demonstrate that CoreGen achieves industry-competitive performance.

Silicon-on-insulator devices are widely utilized in high-performance and high-reliability fields, facing challenges from self-heating effects (SHEs). However, research on the heat dissipation path closely related to SHEs remains incomplete. This paper initiates an in-depth analysis of thermal effects involving the fine structures within the heat dissipation path, using ultrafast pulse I–V measurements combined with thermal simulations. It is found in practical processes that the SHEs of scaled-down devices decreased by 40% rather than increased. Research shows the improvement is attributed to the reduction in the thickness of the buried oxide layer between different generations of processes, and the decrease in thermal sensitivity. Based on the two-stage SHE mechanism, the study clarifies for the first time that the box layer mainly affects first-stage heat dissipation, and the main timescale of impact is about the first 100 ns. In addition, the heat dissipation contact capability can effectively affect the temperature rise of first-stage SHEs. For the first time, we reveal that the TiN barrier layer with low thermal conductivity is the key factor limiting heat dissipation through contact. This study represents the crucial step toward a comprehensive investigation of SHEs, offering substantial support for device modeling.

The electrical performance of high-precision analog and digital circuits in MOSFETs is highly sensitive to temperature changes. Here, by studying the stability of electrical characteristics such as OFF-state leakage current, saturation current, and transconductance efficiency of fully depleted silicon-on-insulator (FDSOI) and partially depleted silicon-on-insulator (PDSOI) in the temperature range of 25 $^{\circ}$ C–300 $^{\circ}$ C, we proposed a new semiconductor-parameter-temperature-increment (SPTI) model. Within this SPTI model, it can clarify the influence of high-temperature electrical parameters, $\alpha_{\textit{T}}$ and $\beta_{\textit{T}}$ , on the stability of the electrical characteristics of FDSOI and PDSOI. Thus, it helps in understanding the differences in the stability of electrical characteristics between the two devices. In addition, the SPTI model can also be used to obtain the design domain of the electrical characteristics for FDSOI and PDSOI. More importantly, a compromise method based on the design parameter $\gamma$ can be obtained to effectively improve the electrical characteristics and the stability of the two devices.

The ongoing trend towards miniaturization and increased packaging density has exacerbated the reliability problem of Au-Al heterogeneous metal bonding structures in high-temperature environments, where extreme temperatures and high current pose a serious challenge. In order to address this issue, the present study aims to investigate the electromigration reliability of Au-Al bonding by comparing the conventional heterogeneous contacts with OPM structures, which are homogeneous contacts. A novel bonding layout was developed to precisely detect the resistance and obtain stage changes in electromigration. The experimental results demonstrated that the relative resistance shift of Au-Al bonding at 250 °C was 98.7%, while CrAu and NiPdAu OPM structures exhibited only 46.1% and 2.93% shifts, which suggests that the reliability of OPM structures was improved by a factor of 2.14 and 33.6, respectively. The degradation of Au-Al bonding was attributed to the large cracks observed at the bonding interface and lateral consumption of Al elements. In contrast, OPM structures only exhibited tiny voids and maintained a better bonding state overall, indicating that homogeneous metal contacts have better immunity to electromigration. Furthermore, this study also observed the polarity effect of electromigration and analyzed the impact of NiPdAu thickness on reliability. Overall, this research provides a novel approach and an insightful theoretical reference for addressing the bottleneck of high-temperature electromigration reliability in high-temperature sensor packaging.

In this work, we present new evidence of the physical mechanism behind the generation of low-frequency noise with high interface-trap density by measuring the low-frequency noise magnitudes of partially depleted (PD) silicon-on-insulator (SOI) NMOSFETs as a function of irradiation dose. We measure the DC electrical characteristics of the devices at different irradiation doses and separate the threshold-voltage shifts caused by the oxide-trap charge and interface-trap charge. Moreover, the increased densities of the oxide-trap charge projected to the Si/SiO₂ interface and interface-trap charge are calculated. The results of our experiment suggest that the magnitudes of low-frequency noise do not necessarily increase with the increase in border-trap density. A novel physical explanation for the low-frequency noise in SOI-NMOSFETs with high interface-trap density is proposed. We reveal that the presence of high-density interface traps after irradiation has a repressing effect on the generation of low-frequency noise. Furthermore, the exchange of some carriers between border traps and interface traps can cause a decrease in the magnitude of low-frequency noise when the interface-trap density is high.

Partially-depleted silicon-on-insulator (PDSOI) MOSFETs with full dielectric isolation structure are widely used in the high temperature field of 225 °C, but affected by the threshold voltage and carrier mobility, the saturated output current has a rate of change as high as 24.9% at 25 °C–300 °C, which will reduce the working speed and accuracy of the analog circuit. This paper studies the high temperature output current characteristics of ultra-thin body and buried oxide (UTBB) fully-depleted silicon-on-insulator (FDSOI) MOSFETs with the 28 nm low voltage threshold structure. The experimental results show that when the gate voltage of the device is constant, the saturation current change of 28 nm short-channel FDSOI device is 1.93% in the temperature range from 25 °C to 300 °C, which is 12.9 times more stable than that of 0.13 μm PDSOI device, 4.5 times and 8.4 times higher than that of 0.3 μm and 2 μm long-channel FDSOI device. When the gate voltage of the device drifts from the zero-temperature coefficient (ZTC) point by ±10%–±20%, the output current change of the short-channel FDSOI device is still the lowest. It is proved by theory and simulation that the low temperature change rate of the carrier velocity of the short-channel FDSOI device is the main factor affecting the stability of the output current. From the analysis of the saturation current model and the ZTC operating point, reducing the gate operating voltage of the device or increasing the threshold voltage of the device can further improve the stability of the output current at high temperatures. The research in this paper proves that the 28 nm UTBB FDSOI device has good high temperature saturation current stability, which can well meet the output current stability requirements of high temperature analog circuits.

The self-heating effect (SHE) of silicon-on-insulator (SOI) MOSFETs brings challenges to the measurement and modeling of transient electrothermal characteristics. For the first time, this study obtains the transient two-stage thermal equivalent RC network of SOI MOSFETs by nano double-pulse measurement combined with network identification by a deconvolution (NID) method. The two-stage model provides a comprehensive reference for the accumulation of residual heat under dynamic operation. We reveal that since the oxide layer acts as a thermal reservoir, the heat dissipation process can be divided into three phases according to thermal time constants. The results of geometry dependence of thermal parameters show that the gate length and width-to-length ratio ( ${W}/{L}$ ) increase: the thermal resistance trend of both stages decreases, the one-stage thermal time constant increases, but the two-stage thermal time constant decreases. Also, as the scaling of device dimension and mutual thermal coupling, the thermal transient response boosts significantly.

Partially depleted silicon-on-insulator (PDSOI) MOSFETs are widely used in 225 °C high-temperature electronic system applications with integrated circuits. But the process node stays at 0.5 µm for a long time and no further breakthrough can be achieved. This paper reports the high-temperature characteristics of 28 nm ultra-thin body and box fully depleted SOI (FDSOI) CMOS transistors with low threshold voltage (LVT) structure. Experimental results demonstrate that V _t shift changes with temperature as low as 0.59 mV °C⁻¹, the subthreshold slope (SS) is 145.35 mV dec⁻¹ at 300 °C, and the related parameters are optimized by 3.7 times and 2.2 times respectively compared with 0.13 µm PDSOI. Combined with theoretical analysis, it is proved that the ultra-body FDSOI has an LVT drift rate and better SS than 0.13 µm PDSOI at high temperature. The advantage of this performance is mainly due to the difference between α VT α _VT and β _VT coefficients related to the back gate effect. Under negative back-gate bias, the I _on/l _off ratio can be increased by two orders of magnitude without affecting V _t shift changes with temperature, this proves that the FDSOI is capable of high-temperature applications above 300 °C. This paper provides substantial support for future high-temperature system integrated circuits from the micro-scale to the nano-scale.

In this work, the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, is investigated. The multi-snapback phenomenon was observed under the transmission line pulsing (TLP) test system. It was found that gate voltage and inserting shallow trench isolation (STI) can significantly affect the trigger voltage and holding voltage. The underlying physical mechanism related to the multi-snapback phenomenon and the effects of gate voltage on the critical parameters was investigated through the experimental results and the assistance of technology computer-aided design (TCAD) simulations. The adjustments of gate voltage and STI on the critical ESD parameters of the device provide an effective design idea for low-voltage ESD protection in the SOI BCD process.