Julio Costella Vicenzi
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Julio Costella Vicenzi has a total of 10 co-authors. Here are the top co-authors by number of shared publications:
- Antonio Carlos Schneider Beck
Federal University of Rio Grande do Sul
1 shared publication - Arthur Francisco Lorenzon
Federal University of Rio Grande do Sul
1 shared publication - Carlos Gabriel de Araujo Gewehr
School of Technology, Pontifical Catholic University of Rio Grande do Sul (PUCRS), Porto Alegre, Brazil
1 shared publication - Everton Alceu Carara
Universidade Federal de Santa Maria, Santa Maria, RS, Brazil
1 shared publication - Guilherme Korol
Department of Computer Science, TU Dresden, Dresden, Germany
1 shared publication - Leonardo Londero de Oliveira
Universidade Federal de Santa Maria, Santa Maria, RS, Brazil
1 shared publication
Latest Publications
- 22 August 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-6
On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments
Cloud Environments have been constantly adopting collaborative CPU-FPGA architectures to accelerate applications by partitioning the execution of their kernels across both devices. However, exploiting the optimization techniques that both archi-tectures offer is challenging, so they must be smartly employed depending on the application at hand and the target optimization (e.g., performance or energy). Given that, this work investigates the impact of collaboratively applying thread throttling (i.e. artificially decreasing the number of active threads) on the CPU side and HLS (High-Level Synthesis)-versioning on the FPGA side. We use a multi-tenant Cloud service as our object of study, where sequence of application requests with different priorities result in DAGs of application kernels that must be executed over the heterogeneous architecture. We show that by synergistically applying thread throttling and HLS-versioning to the incoming kernels may improve the Energy-Dealy product in up to 41x over the default and non-optimized execution.
- 22 August 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-6
On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments
Cloud Environments have been constantly adopting collaborative CPU-FPGA architectures to accelerate applications by partitioning the execution of their kernels across both devices. However, exploiting the optimization techniques that both archi-tectures offer is challenging, so they must be smartly employed depending on the application at hand and the target optimization (e.g., performance or energy). Given that, this work investigates the impact of collaboratively applying thread throttling (i.e. artificially decreasing the number of active threads) on the CPU side and HLS (High-Level Synthesis)-versioning on the FPGA side. We use a multi-tenant Cloud service as our object of study, where sequence of application requests with different priorities result in DAGs of application kernels that must be executed over the heterogeneous architecture. We show that by synergistically applying thread throttling and HLS-versioning to the incoming kernels may improve the Energy-Dealy product in up to 41x over the default and non-optimized execution.
- 6 August 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test
- Vol. 39 (2) , 7-14
Dedicated Shapelet Distance Engine for Time-Series Classification
Shapelet-based methods have emerged as accurate and interpretable tools for time-series classification in machine learning applications. Although these methods find wide applicability, nowadays their use is restricted due to the heavy computational burden associated with numerous computations of z-score normalization and Euclidean distance. The current article addresses this issue with the proposal of a parameterizable parallel hardware accelerator to perform the aforementioned computations. Results show that our dedicated shapelet distance engine can significantly reduce the runtime when compared with a software implementation, achieving speedups of up to five times in terms of clock cycles.
- 6 August 2021
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Design & Test
- Vol. 39 (2) , 7-14
Dedicated Shapelet Distance Engine for Time-Series Classification
Shapelet-based methods have emerged as accurate and interpretable tools for time-series classification in machine learning applications. Although these methods find wide applicability, nowadays their use is restricted due to the heavy computational burden associated with numerous computations of z-score normalization and Euclidean distance. The current article addresses this issue with the proposal of a parameterizable parallel hardware accelerator to perform the aforementioned computations. Results show that our dedicated shapelet distance engine can significantly reduce the runtime when compared with a software implementation, achieving speedups of up to five times in terms of clock cycles.