Guilherme Korol
Current Organizations / Institutes
The organizations/institutes from the scholar's latest article
Previous Organizations / Institutes
The organizations / institutes from the scholar's other articles in the past ten years
Guilherme Korol has a total of 12 co-authors. Here are the top co-authors by number of shared publications:
- Antonio Carlos Schneider Beck
Federal University of Rio Grande do Sul
5 shared publications - Mateus Beck Rutzig
UFSM
4 shared publications - Michael Guilherme Jordan
Federal University of Rio Grande do Sul
4 shared publications - Arthur Francisco Lorenzon
Federal University of Rio Grande do Sul
2 shared publications Antonio Carlos Schneider Beck
1 shared publicationBernardo Neuhaus Lignati
1 shared publication
Latest Publications
- 4 March 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 33 (9) , 2382-2394
IoT-Edge Splitting With Pruned Early-Exit CNNs for Adaptive Inference
Deep neural networks (DNNs) are driving the Internet of Things (IoT) revolution. To manage latency and privacy concerns in this domain, IoT devices may offload partial or full DNN processing to nearby edge servers rather than relying only on the cloud. In this scenario, while field-programmable gate arrays (FPGAs) are efficient and provide flexibility for these resource-constrained IoT and edge devices, runtime optimizations like pruning and early exit can deliver further improvements. However, they need to be applied with careful design, since offloading and split computing may require constant synchronization of such dynamic DNN models. With that in mind, this article introduces a framework that automatically constructs inference platforms combining pruning and early exit with FPGA-based offloading. It addresses the latency-power-accuracy tradeoff, adapting inference to the unpredictable conditions of IoT-edge environments. Using convolutional neural networks (CNNs) as a case study, it achieves a reduction of up to$1.6\times $ in latency and a$3.9\times $ improvement in power efficiency, with minimal accuracy loss.- 4 March 2025
- Published by Institute of Electrical and Electronics Engineers (IEEE) in IEEE Transactions on Very Large Scale Integration (VLSI) Systems
- Vol. 33 (9) , 2382-2394
IoT-Edge Splitting With Pruned Early-Exit CNNs for Adaptive Inference
Deep neural networks (DNNs) are driving the Internet of Things (IoT) revolution. To manage latency and privacy concerns in this domain, IoT devices may offload partial or full DNN processing to nearby edge servers rather than relying only on the cloud. In this scenario, while field-programmable gate arrays (FPGAs) are efficient and provide flexibility for these resource-constrained IoT and edge devices, runtime optimizations like pruning and early exit can deliver further improvements. However, they need to be applied with careful design, since offloading and split computing may require constant synchronization of such dynamic DNN models. With that in mind, this article introduces a framework that automatically constructs inference platforms combining pruning and early exit with FPGA-based offloading. It addresses the latency-power-accuracy tradeoff, adapting inference to the unpredictable conditions of IoT-edge environments. Using convolutional neural networks (CNNs) as a case study, it achieves a reduction of up to$1.6\times $ in latency and a$3.9\times $ improvement in power efficiency, with minimal accuracy loss.- 11 July 2023
- Published by Elsevier in Integration
- Vol. 93
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems
- 11 July 2023
- Published by Elsevier in Integration
- Vol. 93
MVSym: Efficient symbiotic exploitation of HLS-kernel multi-versioning for collaborative CPU-FPGA cloud systems
- 27 April 2023
- Published by Springer Nature
- p. 95-106
Adaptive Inference for FPGA-Based 5G Automatic Modulation Classification
- 27 April 2023
- Published by Springer Nature
- p. 95-106
Adaptive Inference for FPGA-Based 5G Automatic Modulation Classification
- 22 August 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-6
On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments
Cloud Environments have been constantly adopting collaborative CPU-FPGA architectures to accelerate applications by partitioning the execution of their kernels across both devices. However, exploiting the optimization techniques that both archi-tectures offer is challenging, so they must be smartly employed depending on the application at hand and the target optimization (e.g., performance or energy). Given that, this work investigates the impact of collaboratively applying thread throttling (i.e. artificially decreasing the number of active threads) on the CPU side and HLS (High-Level Synthesis)-versioning on the FPGA side. We use a multi-tenant Cloud service as our object of study, where sequence of application requests with different priorities result in DAGs of application kernels that must be executed over the heterogeneous architecture. We show that by synergistically applying thread throttling and HLS-versioning to the incoming kernels may improve the Energy-Dealy product in up to 41x over the default and non-optimized execution.
- 22 August 2022
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 1-6
On the benefits of Collaborative Thread Throttling and HLS-Versioning in CPU-FPGA Environments
Cloud Environments have been constantly adopting collaborative CPU-FPGA architectures to accelerate applications by partitioning the execution of their kernels across both devices. However, exploiting the optimization techniques that both archi-tectures offer is challenging, so they must be smartly employed depending on the application at hand and the target optimization (e.g., performance or energy). Given that, this work investigates the impact of collaboratively applying thread throttling (i.e. artificially decreasing the number of active threads) on the CPU side and HLS (High-Level Synthesis)-versioning on the FPGA side. We use a multi-tenant Cloud service as our object of study, where sequence of application requests with different priorities result in DAGs of application kernels that must be executed over the heterogeneous architecture. We show that by synergistically applying thread throttling and HLS-versioning to the incoming kernels may improve the Energy-Dealy product in up to 41x over the default and non-optimized execution.
- 4 November 2020
- Published by Springer Nature in Design Automation for Embedded Systems
- Vol. 25 (2) , 135-160
Dynamic concurrency throttling on NUMA systems and data migration impacts
- 4 November 2020
- Published by Springer Nature in Design Automation for Embedded Systems
- Vol. 25 (2) , 135-160
Dynamic concurrency throttling on NUMA systems and data migration impacts
- 1 November 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 626-629
Power-Aware Phase Oriented Reconfigurable Architecture
CGRAs have emerged as an energy-efficient solution providing on-demand acceleration in heterogeneous systems. However, the diversity and unpredictability of workloads pose a challenge in managing CGRA resources whenever a power budget has to be met. This work proposes a hardware module to, transparently and automatically, perform power-gating of CGRA resources. The module implements a greedy algorithm to find the near-optimal CGRA size, which is particular to the current application phase, so part of the CGRA can be switched off with no (or little) performance penalty. As soon as a change in program phase is detected, the proposed method can adapt the CGRA to the phase in progress. Results show an average of 29% power reduction and 43% energy reduction with 1.4% performance penalty compared to a CGRA with no power management.
- 1 November 2019
- Published by Institute of Electrical and Electronics Engineers (IEEE)
- p. 626-629
Power-Aware Phase Oriented Reconfigurable Architecture
CGRAs have emerged as an energy-efficient solution providing on-demand acceleration in heterogeneous systems. However, the diversity and unpredictability of workloads pose a challenge in managing CGRA resources whenever a power budget has to be met. This work proposes a hardware module to, transparently and automatically, perform power-gating of CGRA resources. The module implements a greedy algorithm to find the near-optimal CGRA size, which is particular to the current application phase, so part of the CGRA can be switched off with no (or little) performance penalty. As soon as a change in program phase is detected, the proposed method can adapt the CGRA to the phase in progress. Results show an average of 29% power reduction and 43% energy reduction with 1.4% performance penalty compared to a CGRA with no power management.