Fabia Farlin Athena

We demonstrate a gate-dielectric engineering approach leveraging an ultrathin, atomic-layer-deposited silicon oxide interfacial layer (SiL) between the amorphous oxide semiconductor (AOS) channel and the high-k gate dielectric. SiL positively shifts the threshold voltage (V_T) of AOS transistors, providing at least four distinct V_T levels with a maximum increase of 500 mV. It achieves stable V_T control without significantly degrading critical device parameters such as mobility and on-state current, all while keeping the process temperature below 225 °C and requiring no additional heat treatment to activate the dipole. Positive-bias temperature instability tests at 85 °C indicate a significant reduction in negative V_T shifts for SiL-integrated devices, highlighting the enhanced reliability. Incorporating this SiL gate stack into two-transistor gain-cell (GC) memory maintains a more stable storage node voltage (V_SN) (reduces V_SN drop by 67%), by limiting unwanted charge losses. SiL-engineered GCs also reach retention times up to 10000 s at room temperature and reduce standby leakage current by 3 orders of magnitude relative to baseline device, substantially lowering refresh energy consumption.

As we move beyond the era of transistor miniaturization, back-end-of-line-compatible transistors that can be stacked monolithically in the third dimension promise improved performance for low-power electronics. In advanced transistor architectures, such as gate-all-around nanosheets, the conventional channel-first process involves depositing dielectrics directly onto the channel. Atomic layer deposition of gate dielectrics on back-end-of-line compatible channel materials, such as amorphous oxide semiconductors, can induce defects or cause structural modifications that degrade electrical performance. While post-deposition annealing can partially repair this damage, it often degrades other device metrics. We report a novel channel-last concept that prevents such damage. Channel-last gate-all-around self-aligned transistors with amorphous oxide-semiconductor channels exhibit high on-state current ($>$ 1 mA/$μ$m) and low subthreshold swing (minimum of 63 mV/dec) without the need for post-deposition processing. This approach offers a general, scalable pathway for transistors with atomic layer deposited channel materials, enabling the future of low-power three-dimensional electronics.

Since the initial synthesis of van der Waals 2D indium selenide is first documented in 1957, five distinct polymorphs and their corresponding polytypes are identified. In this study, a unique phase of indium selenide is reported via Scanning Transmission Electron Microscopy (STEM) analysis in the synthesized large‐area films – which is named the phase. The quintuple layers of the phase, characterized by a unique zigzag atomic configuration with unequal indium‐selenium bond lengths from the middle selenium atom, are distinct from any other previously reported phase of indium selenide. Cross‐sectional STEM analysis has revealed that the layers exhibit intralayer shifting. It is found that indium selenide films with layers display electric‐field‐induced switchable polarization characteristic of ferroelectric materials, suggesting the breaking of the inversion symmetry. Experimental observations of nonlinear optical phenomena – Second Harmonic Generation (SHG) responses further support this conclusion. This study reports a phase of indium selenide showing ferroelectricity over large areas at room temperature in a low‐dimensional limit.

A Ti₂AlN MAX phase layered thin film electrode and oxygen getter layer for HfO₂‐based two‐terminal memristors is presented. The Ti₂AlN/HfO_x/Ti memristor devices exhibit enhanced resistive switching performance, including an ultra‐low reset current density (< 10⁻⁸ MΩ cm²), substantial on‐off ratio (≈ 6000), excellent multi‐level functionality (≈ 9 distinct states), impressive retention (up to 300 °C), and robust endurance (>200 million) as compared to conventional TiN and other alternative materials based memristors. Experimental measurements and modeling suggest that the distinctive combination of low thermal conductivity, high electrical conductivity, and unique ultra‐thin layer‐by‐layer structure of the Ti₂AlN MAX phase thin film contribute to this exceptional performance with good reproducibility and stability. The results demonstrate for the first‐time the potential of this innovative sputtered MAX phase material for engineering energy‐efficient, high‐density non‐volatile digital, and analog memory devices aimed toward next‐generation sustainable artificial intelligence.

Changes in the resistance of Ti/HfOx synapses are known to be governed by a thin-oxide barrier associated with the oxidation/reduction of a Hf-rich conducting filament (CF). However, experimental characterization of the CF is challenging. Critical physical properties and processes, such as the barrier location, time-dependent thickness during analog pulsing, and the temperature-effect on current, need to be better established. In this work, a compact model based on Trap-Assisted-Tunneling and Ohmic transport is utilized to analyze the analog switching of HfOx synapses. The model agrees well with the experimentally observed current–voltage relation and its temperature dependence. The extracted barrier heights during analog pulsing are consistent with a barrier situated near the reset anode; the electrode is opposite to the Ti oxygen-reservoir layer. A Finite Element Analysis simulation, which incorporates oxygen-vacancy migration, independently supports this conclusion. The model further permits extraction of the barrier thickness in relation to the analog pulses.

In this article, we propose an electrical bias technique to recover the accuracy of a degraded $\text{HfO}_{\textit{x}}$ -based resistive random access memory (ReRAM) array in deep neural network (DNN) training. We simulate degradation through the application of ${\sim} \text{10}^\text{4}$ pulses having high pulse amplitude, resulting in a fatigued ReRAM array that fails to converge during training. We propose a novel technique, recovery stabilization (ReSta) , which can recover the array accuracy up to the level it was before the fatigue was introduced. After using the proposed controlled recovery technique, we obtain an accuracy of 98% on the reduced Modified National Institute of Standard and Technology (MNIST) classification task, approaching a floating point baseline. This work demonstrates a viable pathway to recover the performance of the fatigued ReRAM crossbar arrays in in-memory DNN training.

HfO_x-based synapses are widely accepted as a viable candidate for both in-memory and neuromorphic computing. Resistance change in oxide-based synapses is caused by the motion of oxygen vacancies. HfO_x-based synapses typically demonstrate an abrupt nonlinear resistance change under positive bias application (set), limiting their viability as analog memory. In this work, a thin barrier layer of AlO_x or SiO_x is added to the bottom electrode/oxide interface to slow the migration of oxygen vacancies. Electrical results show that the resistance change in HfO_x/SiO_x devices is more controlled than the HfO_x devices during the set. While the on/off ratio for the HfO_x/SiO_x devices is still large (∼10), it is shown to be smaller than that of HfO_x/AlO_x and HfO_x devices. Finite element modeling suggests that the slower oxygen vacancy migration in HfO_x/SiO_x devices during reset results in a narrower rupture region in the conductive filament. The narrower rupture region causes a lower high resistance state and, thus, a smaller on/off ratio for the HfO_x/SiO_x devices. Overall, the results show that slowing the motion of oxygen vacancies in the barrier layer devices improves the resistance change during the set but lowers the on/off ratio.

As the demand for computing applications capable of processing large datasets increases, there is a growing need for new in-memory computing technologies. Oxide-based resistive random-access memory (RRAM) devices are promising candidates for such applications because of their industry readiness, endurance, and switching ratio. These analog devices, however, suffer from poor linearity and asymmetry in their analog resistance change. Various reports have found that the temperature in RRAM devices increases locally by more than 1000 K during operation. Therefore, temperature control is of paramount importance for controlling their resistance. In this study, scanning thermal microscopy is used to map the temperature of Au/Ti/HfOx/Au devices at a steady power state and to measure temperature dynamics of the top electrode above the filament location during both resistive switching loops and voltage pulsing. These measurements are used to verify the thermal parameters of a multiphysics finite elements model. The model is then used to understand the impact of thermal conductivities and boundary conductances of constituent materials on resistance change during the first reset pulse in RRAM devices. It is found that the resistance change can be reduced significantly when the temperature in the titanium capping layer is reduced. We find that the greatest temperature reduction and, therefore, the lowest resistance change in the device are afforded by capping layers with increased thermal conductivities. This work links thermal properties to the resistance change in RRAM devices, providing critical insights into engineering devices with improved switching dynamics.